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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
368 lines
12 KiB
ArmAsm
368 lines
12 KiB
ArmAsm
/*
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* Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <services/arm_arch_svc.h>
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.globl wa_cve_2017_5715_bpiall_vbar
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#define EMIT_BPIALL 0xee070fd5
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#define EMIT_SMC 0xe1600070
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#define ESR_EL3_A64_SMC0 0x5e000000
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.macro apply_cve_2017_5715_wa _from_vector
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/*
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* Save register state to enable a call to AArch32 S-EL1 and return
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* Identify the original calling vector in w2 (==_from_vector)
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* Use w3-w6 for additional register state preservation while in S-EL1
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*/
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/* Save GP regs */
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
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stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
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stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
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stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
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stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
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stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
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stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
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stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
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stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
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stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
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stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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/* Identify the original exception vector */
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mov w2, \_from_vector
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/* Preserve 32-bit system registers in GP registers through the workaround */
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mrs x3, esr_el3
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mrs x4, spsr_el3
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mrs x5, scr_el3
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mrs x6, sctlr_el1
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/*
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* Preserve LR and ELR_EL3 registers in the GP regs context.
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* Temporarily use the CTX_GPREG_SP_EL0 slot to preserve ELR_EL3
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* through the workaround. This is OK because at this point the
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* current state for this context's SP_EL0 is in the live system
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* register, which is unmodified by the workaround.
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*/
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mrs x7, elr_el3
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stp x30, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/*
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* Load system registers for entry to S-EL1.
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*/
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/* Mask all interrupts and set AArch32 Supervisor mode */
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movz w8, SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, SPSR_AIF_MASK)
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/* Switch EL3 exception vectors while the workaround is executing. */
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adr x9, wa_cve_2017_5715_bpiall_ret_vbar
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/* Setup SCTLR_EL1 with MMU off and I$ on */
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ldr x10, stub_sel1_sctlr
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/* Land at the S-EL1 workaround stub */
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adr x11, aarch32_stub
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/*
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* Setting SCR_EL3 to all zeroes means that the NS, RW
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* and SMD bits are configured as expected.
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*/
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msr scr_el3, xzr
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msr spsr_el3, x8
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msr vbar_el3, x9
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msr sctlr_el1, x10
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msr elr_el3, x11
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eret
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.endm
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/* ---------------------------------------------------------------------
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* This vector table is used at runtime to enter the workaround at
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* AArch32 S-EL1 for Sync/IRQ/FIQ/SError exceptions. If the workaround
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* is not enabled, the existing runtime exception vector table is used.
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* ---------------------------------------------------------------------
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*/
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vector_base wa_cve_2017_5715_bpiall_vbar
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_sync_exception_sp_el0
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b sync_exception_sp_el0
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nop /* to force 8 byte alignment for the following stub */
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/*
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* Since each vector table entry is 128 bytes, we can store the
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* stub context in the unused space to minimize memory footprint.
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*/
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stub_sel1_sctlr:
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.quad SCTLR_AARCH32_EL1_RES1 | SCTLR_I_BIT
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aarch32_stub:
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.word EMIT_BPIALL
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.word EMIT_SMC
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end_vector_entry bpiall_sync_exception_sp_el0
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vector_entry bpiall_irq_sp_el0
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b irq_sp_el0
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end_vector_entry bpiall_irq_sp_el0
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vector_entry bpiall_fiq_sp_el0
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b fiq_sp_el0
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end_vector_entry bpiall_fiq_sp_el0
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vector_entry bpiall_serror_sp_el0
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b serror_sp_el0
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end_vector_entry bpiall_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_sync_exception_sp_elx
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b sync_exception_sp_elx
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end_vector_entry bpiall_sync_exception_sp_elx
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vector_entry bpiall_irq_sp_elx
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b irq_sp_elx
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end_vector_entry bpiall_irq_sp_elx
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vector_entry bpiall_fiq_sp_elx
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b fiq_sp_elx
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end_vector_entry bpiall_fiq_sp_elx
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vector_entry bpiall_serror_sp_elx
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b serror_sp_elx
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end_vector_entry bpiall_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_sync_exception_aarch64
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apply_cve_2017_5715_wa 1
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end_vector_entry bpiall_sync_exception_aarch64
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vector_entry bpiall_irq_aarch64
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apply_cve_2017_5715_wa 2
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end_vector_entry bpiall_irq_aarch64
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vector_entry bpiall_fiq_aarch64
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apply_cve_2017_5715_wa 4
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end_vector_entry bpiall_fiq_aarch64
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vector_entry bpiall_serror_aarch64
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apply_cve_2017_5715_wa 8
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end_vector_entry bpiall_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_sync_exception_aarch32
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apply_cve_2017_5715_wa 1
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end_vector_entry bpiall_sync_exception_aarch32
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vector_entry bpiall_irq_aarch32
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apply_cve_2017_5715_wa 2
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end_vector_entry bpiall_irq_aarch32
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vector_entry bpiall_fiq_aarch32
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apply_cve_2017_5715_wa 4
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end_vector_entry bpiall_fiq_aarch32
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vector_entry bpiall_serror_aarch32
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apply_cve_2017_5715_wa 8
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end_vector_entry bpiall_serror_aarch32
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/* ---------------------------------------------------------------------
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* This vector table is used while the workaround is executing. It
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* installs a simple SMC handler to allow the Sync/IRQ/FIQ/SError
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* workaround stubs to enter EL3 from S-EL1. It restores the previous
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* EL3 state before proceeding with the normal runtime exception vector.
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* ---------------------------------------------------------------------
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*/
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vector_base wa_cve_2017_5715_bpiall_ret_vbar
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200 (UNUSED)
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_ret_sync_exception_sp_el0
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b report_unhandled_exception
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end_vector_entry bpiall_ret_sync_exception_sp_el0
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vector_entry bpiall_ret_irq_sp_el0
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b report_unhandled_interrupt
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end_vector_entry bpiall_ret_irq_sp_el0
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vector_entry bpiall_ret_fiq_sp_el0
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b report_unhandled_interrupt
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end_vector_entry bpiall_ret_fiq_sp_el0
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vector_entry bpiall_ret_serror_sp_el0
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b report_unhandled_exception
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end_vector_entry bpiall_ret_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400 (UNUSED)
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_ret_sync_exception_sp_elx
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b report_unhandled_exception
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end_vector_entry bpiall_ret_sync_exception_sp_elx
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vector_entry bpiall_ret_irq_sp_elx
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b report_unhandled_interrupt
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end_vector_entry bpiall_ret_irq_sp_elx
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vector_entry bpiall_ret_fiq_sp_elx
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b report_unhandled_interrupt
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end_vector_entry bpiall_ret_fiq_sp_elx
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vector_entry bpiall_ret_serror_sp_elx
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b report_unhandled_exception
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end_vector_entry bpiall_ret_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600 (UNUSED)
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_ret_sync_exception_aarch64
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b report_unhandled_exception
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end_vector_entry bpiall_ret_sync_exception_aarch64
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vector_entry bpiall_ret_irq_aarch64
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b report_unhandled_interrupt
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end_vector_entry bpiall_ret_irq_aarch64
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vector_entry bpiall_ret_fiq_aarch64
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b report_unhandled_interrupt
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end_vector_entry bpiall_ret_fiq_aarch64
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vector_entry bpiall_ret_serror_aarch64
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b report_unhandled_exception
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end_vector_entry bpiall_ret_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry bpiall_ret_sync_exception_aarch32
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/*
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* w2 indicates which SEL1 stub was run and thus which original vector was used
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* w3-w6 contain saved system register state (esr_el3 in w3)
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* Restore LR and ELR_EL3 register state from the GP regs context
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*/
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ldp x30, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/* Apply the restored system register state */
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msr esr_el3, x3
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msr spsr_el3, x4
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msr scr_el3, x5
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msr sctlr_el1, x6
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msr elr_el3, x7
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/*
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* Workaround is complete, so swap VBAR_EL3 to point
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* to workaround entry table in preparation for subsequent
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* Sync/IRQ/FIQ/SError exceptions.
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*/
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adr x0, wa_cve_2017_5715_bpiall_vbar
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msr vbar_el3, x0
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/*
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* Restore all GP regs except x2 and x3 (esr). The value in x2
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* indicates the type of the original exception.
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*/
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
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ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
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ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
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ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
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ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
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ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
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ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
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ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
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ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
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ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
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ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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/* Fast path Sync exceptions. Static predictor will fall through. */
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tbz w2, #0, workaround_not_sync
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/*
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* Check if SMC is coming from A64 state on #0
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* with W0 = SMCCC_ARCH_WORKAROUND_1 or W0 = SMCCC_ARCH_WORKAROUND_3
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*
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* This sequence evaluates as:
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* (W0==SMCCC_ARCH_WORKAROUND_1) || (W0==SMCCC_ARCH_WORKAROUND_3) ?
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* (ESR_EL3==SMC#0) : (NE)
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* allowing use of a single branch operation
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*/
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orr w2, wzr, #SMCCC_ARCH_WORKAROUND_1
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cmp w0, w2
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orr w2, wzr, #SMCCC_ARCH_WORKAROUND_3
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ccmp w0, w2, #4, ne
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mov_imm w2, ESR_EL3_A64_SMC0
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ccmp w3, w2, #0, eq
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/* Static predictor will predict a fall through */
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bne 1f
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eret
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1:
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/* restore x2 and x3 and continue sync exception handling */
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b bpiall_ret_sync_exception_aarch32_tail
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end_vector_entry bpiall_ret_sync_exception_aarch32
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vector_entry bpiall_ret_irq_aarch32
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b report_unhandled_interrupt
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/*
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* Post-workaround fan-out for non-sync exceptions
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*/
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workaround_not_sync:
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tbnz w2, #3, bpiall_ret_serror
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tbnz w2, #2, bpiall_ret_fiq
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/* IRQ */
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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b irq_aarch64
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bpiall_ret_fiq:
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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b fiq_aarch64
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bpiall_ret_serror:
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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b serror_aarch64
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end_vector_entry bpiall_ret_irq_aarch32
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vector_entry bpiall_ret_fiq_aarch32
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b report_unhandled_interrupt
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end_vector_entry bpiall_ret_fiq_aarch32
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vector_entry bpiall_ret_serror_aarch32
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b report_unhandled_exception
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end_vector_entry bpiall_ret_serror_aarch32
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/*
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* Part of bpiall_ret_sync_exception_aarch32 to save vector space
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*/
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func bpiall_ret_sync_exception_aarch32_tail
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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b sync_exception_aarch64
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endfunc bpiall_ret_sync_exception_aarch32_tail
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