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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
79 lines
1.4 KiB
ArmAsm
79 lines
1.4 KiB
ArmAsm
/*
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* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a12.h>
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#include <cpu_macros.S>
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a12_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A12_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a12_disable_smp
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func cortex_a12_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A12_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a12_enable_smp
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func cortex_a12_reset_func
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b cortex_a12_enable_smp
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endfunc cortex_a12_reset_func
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func cortex_a12_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a12_disable_smp
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endfunc cortex_a12_core_pwr_dwn
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func cortex_a12_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Flush L2 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a12_disable_smp
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endfunc cortex_a12_cluster_pwr_dwn
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declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \
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cortex_a12_reset_func, \
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cortex_a12_core_pwr_dwn, \
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cortex_a12_cluster_pwr_dwn
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