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https://github.com/ARM-software/arm-trusted-firmware.git
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896a5902ec
Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make LOG_LEVEL=50 PLAT=fvp
Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
83 lines
2.9 KiB
C
83 lines
2.9 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_TABLES_AARCH64_H__
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#define __XLAT_TABLES_AARCH64_H__
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#include <arch.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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#if !defined(PAGE_SIZE)
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#error "PAGE_SIZE is not defined."
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#endif
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/*
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* Encode a Physical Address Space size for its use in TCR_ELx.
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*/
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unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr);
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/*
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* In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page
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* granularity. For 4KB granularity, a level 0 table descriptor doesn't support
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* block translation. For 16KB, the same thing happens to levels 0 and 1. For
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* 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture
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* Reference Manual (DDI 0487A.k) for more information.
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*
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* The define below specifies the first table level that allows block
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* descriptors.
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*/
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#if PAGE_SIZE == (4 * 1024)
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# define MIN_LVL_BLOCK_DESC U(1)
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#elif PAGE_SIZE == (16 * 1024) || PAGE_SIZE == (64 * 1024)
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# define MIN_LVL_BLOCK_DESC U(2)
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#endif
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#define XLAT_TABLE_LEVEL_MIN U(0)
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/*
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* Define the architectural limits of the virtual address space in AArch64
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* state.
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*
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* TCR.TxSZ is calculated as 64 minus the width of said address space.
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* The value of TCR.TxSZ must be in the range 16 to 39 [1], which means that
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* the virtual address space width must be in the range 48 to 25 bits.
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*
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* [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* Page 1730: 'Input address size', 'For all translation stages'.
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*/
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#define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MAX))
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#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MIN))
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/*
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* Here we calculate the initial lookup level from the value of the given
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* virtual address space size. For a 4 KB page size,
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* - level 0 supports virtual address spaces of widths 48 to 40 bits;
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* - level 1 from 39 to 31;
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* - level 2 from 30 to 25.
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*
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* Wider or narrower address spaces are not supported. As a result, level 3
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* cannot be used as initial lookup level with 4 KB granularity. See section
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* D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information.
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*
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* For example, for a 35-bit address space (i.e. virt_addr_space_size ==
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* 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table
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* D4-11 in the ARM ARM, the initial lookup level for an address space like that
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* is 1.
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*
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* Note that this macro assumes that the given virtual address space size is
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* valid. Therefore, the caller is expected to check it is the case using the
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* CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
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*/
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#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size) \
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(((_virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \
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? 0 \
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: (((_virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \
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? 1 : 2))
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#endif /* __XLAT_TABLES_AARCH64_H__ */
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