mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
896a5902ec
Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make LOG_LEVEL=50 PLAT=fvp
Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <mmio.h>
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#include <smmu_v3.h>
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/* Test for pending invalidate */
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#define INVAL_PENDING(_base) \
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smmuv3_read_s_init(_base) & SMMU_S_INIT_INV_ALL_MASK
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static inline uint32_t smmuv3_read_s_idr1(uintptr_t base)
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{
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return mmio_read_32(base + SMMU_S_IDR1);
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}
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static inline uint32_t smmuv3_read_s_init(uintptr_t base)
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{
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return mmio_read_32(base + SMMU_S_INIT);
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}
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static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value)
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{
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mmio_write_32(base + SMMU_S_INIT, value);
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}
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/*
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* Initialize the SMMU by invalidating all secure caches and TLBs.
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*
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* Returns 0 on success, and -1 on failure.
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*/
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int smmuv3_init(uintptr_t smmu_base)
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{
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uint32_t idr1_reg;
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/*
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* Invalidation of secure caches and TLBs is required only if the SMMU
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* supports secure state. If not, it's implementation defined as to how
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* SMMU_S_INIT register is accessed.
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*/
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idr1_reg = smmuv3_read_s_idr1(smmu_base);
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if (!((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) &
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SMMU_S_IDR1_SECURE_IMPL_MASK)) {
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return -1;
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}
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/* Initiate invalidation, and wait for it to finish */
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smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK);
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while (INVAL_PENDING(smmu_base))
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;
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return 0;
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}
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