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100d4029a9
Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1 processor core. This issue is present in revisions r0p0, r1p0, and r1p1, and it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe
371 lines
9 KiB
ArmAsm
371 lines
9 KiB
ArmAsm
/*
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* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v1.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #1774420.
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* This applies to revisions r0p0 and r1p0, fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_1774420_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1774420
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cbz x0, 1f
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/* Set bit 53 in CPUECTLR_EL1 */
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mrs x1, NEOVERSE_V1_CPUECTLR_EL1
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orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53
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msr NEOVERSE_V1_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_1774420_wa
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func check_errata_1774420
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/* Applies to r0p0 and r1p0. */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1774420
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #1791573.
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* This applies to revisions r0p0 and r1p0, fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_1791573_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1791573
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cbz x0, 1f
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, NEOVERSE_V1_ACTLR2_EL1
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orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2
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msr NEOVERSE_V1_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_1791573_wa
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func check_errata_1791573
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/* Applies to r0p0 and r1p0. */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1791573
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #1852267.
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* This applies to revisions r0p0 and r1p0, fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_1852267_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1852267
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cbz x0, 1f
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/* Set bit 28 in ACTLR2_EL1 */
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mrs x1, NEOVERSE_V1_ACTLR2_EL1
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orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28
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msr NEOVERSE_V1_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_1852267_wa
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func check_errata_1852267
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/* Applies to r0p0 and r1p0. */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1852267
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #1925756.
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* This applies to revisions <= r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_1925756_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1925756
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cbz x0, 1f
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/* Set bit 8 in CPUECTLR_EL1 */
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mrs x1, NEOVERSE_V1_CPUECTLR_EL1
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orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8
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msr NEOVERSE_V1_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_1925756_wa
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func check_errata_1925756
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/* Applies to <= r1p1. */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1925756
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Erratum #1940577
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* This applies to revisions r1p0 - r1p1 and is open.
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* It also exists in r0p0 but there is no fix in that
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* revision.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_1940577_wa
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/* Compare x0 against revisions r1p0 - r1p1 */
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mov x17, x30
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bl check_errata_1940577
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cbz x0, 1f
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mov x0, #0
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3900002
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #1
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #2
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_1940577_wa
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func check_errata_1940577
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/* Applies to revisions r1p0 - r1p1. */
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mov x1, #0x10
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mov x2, #0x11
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b cpu_rev_var_range
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endfunc check_errata_1940577
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #1966096
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* This applies to revisions r1p0 - r1p1 and is open.
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* It also exists in r0p0 but there is no workaround
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* for that revision.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_1966096_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1966096
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cbz x0, 1f
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/* Apply the workaround. */
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mov x0, #0x3
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msr S3_6_C15_C8_0, x0
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ldr x0, =0xEE010F12
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msr S3_6_C15_C8_2, x0
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ldr x0, =0xFFFF0FFF
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x80000000003FF
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msr S3_6_C15_C8_1, x0
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_1966096_wa
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func check_errata_1966096
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mov x1, #0x10
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mov x2, #0x11
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b cpu_rev_var_range
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endfunc check_errata_1966096
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #2139242.
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* This applies to revisions r0p0, r1p0, and r1p1, it
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* is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_2139242_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2139242
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cbz x0, 1f
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/* Apply the workaround. */
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mov x0, #0x3
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msr S3_6_C15_C8_0, x0
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ldr x0, =0xEE720F14
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msr S3_6_C15_C8_2, x0
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ldr x0, =0xFFFF0FDF
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x40000005003FF
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msr S3_6_C15_C8_1, x0
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_2139242_wa
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func check_errata_2139242
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/* Applies to r0p0, r1p0, r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_2139242
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_v1_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc neoverse_v1_core_pwr_dwn
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/*
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* Errata printing function for Neoverse V1. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func neoverse_v1_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
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report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
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report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
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report_errata ERRATA_V1_1925756, neoverse_v1, 1925756
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report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
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report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
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report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
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ldp x8, x30, [sp], #16
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ret
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endfunc neoverse_v1_errata_report
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#endif
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func neoverse_v1_reset_func
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mov x19, x30
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/* Disable speculative loads */
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msr SSBS, xzr
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isb
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#if ERRATA_V1_1774420
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mov x0, x18
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bl errata_neoverse_v1_1774420_wa
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#endif
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#if ERRATA_V1_1791573
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mov x0, x18
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bl errata_neoverse_v1_1791573_wa
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#endif
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#if ERRATA_V1_1852267
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mov x0, x18
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bl errata_neoverse_v1_1852267_wa
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#endif
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#if ERRATA_V1_1925756
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mov x0, x18
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bl errata_neoverse_v1_1925756_wa
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#endif
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#if ERRATA_V1_1940577
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mov x0, x18
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bl errata_neoverse_v1_1940577_wa
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#endif
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#if ERRATA_V1_1966096
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mov x0, x18
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bl errata_neoverse_v1_1966096_wa
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#endif
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#if ERRATA_V1_2139242
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mov x0, x18
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bl errata_neoverse_v1_2139242_wa
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#endif
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ret x19
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endfunc neoverse_v1_reset_func
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/* ---------------------------------------------
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* This function provides Neoverse-V1 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v1_regs, "aS"
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neoverse_v1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v1_cpu_reg_dump
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adr x6, neoverse_v1_regs
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mrs x8, NEOVERSE_V1_CPUECTLR_EL1
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ret
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endfunc neoverse_v1_cpu_reg_dump
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declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
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neoverse_v1_reset_func, \
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neoverse_v1_core_pwr_dwn
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