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https://github.com/ARM-software/arm-trusted-firmware.git
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ae6542f6c7
This driver is used for the new version of the BSEC peripheral used on STM32MP25. Change-Id: I38ca0db22d06704769c994c6806ccd80b17dde6e Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/*
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* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSEC3_REG_H
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#define BSEC3_REG_H
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#include <lib/utils_def.h>
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/* BSEC REGISTER OFFSET (base relative) */
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#define BSEC_FVR(x) (U(0x000) + 4U * (x))
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#define BSEC_SPLOCK(x) (U(0x800) + 4U * (x))
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#define BSEC_SWLOCK(x) (U(0x840) + 4U * (x))
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#define BSEC_SRLOCK(x) (U(0x880) + 4U * (x))
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#define BSEC_OTPVLDR(x) (U(0x8C0) + 4U * (x))
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#define BSEC_SFSR(x) (U(0x940) + 4U * (x))
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#define BSEC_OTPCR U(0xC04)
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#define BSEC_WDR U(0xC08)
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#define BSEC_SCRATCHR0 U(0xE00)
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#define BSEC_SCRATCHR1 U(0xE04)
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#define BSEC_SCRATCHR2 U(0xE08)
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#define BSEC_SCRATCHR3 U(0xE0C)
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#define BSEC_LOCKR U(0xE10)
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#define BSEC_JTAGINR U(0xE14)
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#define BSEC_JTAGOUTR U(0xE18)
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#define BSEC_DENR U(0xE20)
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#define BSEC_UNMAPR U(0xE24)
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#define BSEC_SR U(0xE40)
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#define BSEC_OTPSR U(0xE44)
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#define BSEC_WRCR U(0xF00)
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#define BSEC_HWCFGR U(0xFF0)
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#define BSEC_VERR U(0xFF4)
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#define BSEC_IPIDR U(0xFF8)
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#define BSEC_SIDR U(0xFFC)
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/* BSEC_OTPCR register fields */
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#define BSEC_OTPCR_ADDR_MASK GENMASK_32(8, 0)
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#define BSEC_OTPCR_ADDR_SHIFT U(0)
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#define BSEC_OTPCR_PROG BIT_32(13)
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#define BSEC_OTPCR_PPLOCK BIT_32(14)
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#define BSEC_OTPCR_LASTCID_MASK GENMASK_32(21, 19)
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#define BSEC_OTPCR_LASTCID_SHIFT U(19)
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/* BSEC_LOCKR register fields */
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#define BSEC_LOCKR_GWLOCK_MASK BIT_32(0)
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#define BSEC_LOCKR_GWLOCK_SHIFT U(0)
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#define BSEC_LOCKR_DENLOCK_MASK BIT_32(1)
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#define BSEC_LOCKR_DENLOCK_SHIFT U(1)
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#define BSEC_LOCKR_HKLOCK_MASK BIT_32(2)
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#define BSEC_LOCKR_HKLOCK_SHIFT U(2)
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/* BSEC_DENR register fields */
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#define BSEC_DENR_LPDBGEN BIT_32(0)
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#define BSEC_DENR_DBGENA BIT_32(1)
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#define BSEC_DENR_NIDENA BIT_32(2)
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#define BSEC_DENR_DEVICEEN BIT_32(3)
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#define BSEC_DENR_HDPEN BIT_32(4)
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#define BSEC_DENR_SPIDENA BIT_32(5)
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#define BSEC_DENR_SPNIDENA BIT_32(6)
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#define BSEC_DENR_DBGSWEN BIT_32(7)
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#define BSEC_DENR_DBGENM BIT_32(8)
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#define BSEC_DENR_NIDENM BIT_32(9)
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#define BSEC_DENR_SPIDENM BIT_32(10)
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#define BSEC_DENR_SPNIDENM BIT_32(11)
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#define BSEC_DENR_CFGSDIS BIT_32(12)
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#define BSEC_DENR_CP15SDIS_MASK GENMASK_32(14, 13)
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#define BSEC_DENR_CP15SDIS_SHIFT U(13)
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#define BSEC_DENR_LPDBGDIS BIT_32(15)
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#define BSEC_DENR_ALL_MSK GENMASK_32(15, 0)
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/* BSEC_SR register fields */
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#define BSEC_SR_BUSY BIT_32(0)
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#define BSEC_SR_HVALID BIT_32(1)
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#define BSEC_SR_RNGERR BIT_32(2)
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#define BSEC_SR_HKWW_MASK GENMASK_32(15, 8)
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#define BSEC_SR_HKWW_SHIFT U(8)
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#define BSEC_SR_NVSTATE_MASK GENMASK_32(31, 26)
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#define BSEC_SR_NVSTATE_SHIFT U(26)
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#define BSEC_SR_NVSTATE_OPEN U(0x16)
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#define BSEC_SR_NVSTATE_CLOSED U(0x0D)
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#define BSEC_SR_NVSTATE_OTP_LOCKED U(0x23)
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/* BSEC_OTPSR register fields */
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#define BSEC_OTPSR_BUSY BIT_32(0)
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#define BSEC_OTPSR_FUSEOK BIT_32(1)
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#define BSEC_OTPSR_HIDEUP BIT_32(2)
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#define BSEC_OTPSR_OTPNVIR BIT_32(4)
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#define BSEC_OTPSR_OTPERR BIT_32(5)
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#define BSEC_OTPSR_OTPSEC BIT_32(6)
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#define BSEC_OTPSR_PROGFAIL BIT_32(16)
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#define BSEC_OTPSR_DISTURBF BIT_32(17)
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#define BSEC_OTPSR_DEDF BIT_32(18)
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#define BSEC_OTPSR_SECF BIT_32(19)
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#define BSEC_OTPSR_PPLF BIT_32(20)
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#define BSEC_OTPSR_PPLMF BIT_32(21)
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#define BSEC_OTPSR_AMEF BIT_32(22)
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/* BSEC_VERR register fields */
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#define BSEC_VERR_MASK GENMASK_32(7, 0)
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#endif /* BSEC3_REG_H */
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