mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
87d3aacc88
Rule 5.1: External identifiers shall be distinct
Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens these names to
make sure they are different.
Fixed for:
LOG_LEVEL=50 PLAT=fvp
Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
599 lines
18 KiB
C
599 lines
18 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <gic_common.h>
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#include <interrupt_props.h>
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#include "../common/gic_common_private.h"
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#include "gicv3_private.h"
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/*
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* Accessor to read the GIC Distributor IGRPMODR corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> IGRPMODR_SHIFT;
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return mmio_read_32(base + GICD_IGRPMODR + (n << 2));
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}
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/*
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* Accessor to write the GIC Distributor IGRPMODR corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> IGRPMODR_SHIFT;
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mmio_write_32(base + GICD_IGRPMODR + (n << 2), val);
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}
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/*
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* Accessor to get the bit corresponding to interrupt ID
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* in GIC Distributor IGRPMODR.
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*/
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unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
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unsigned int reg_val = gicd_read_igrpmodr(base, id);
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return (reg_val >> bit_num) & 0x1;
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}
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/*
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* Accessor to set the bit corresponding to interrupt ID
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* in GIC Distributor IGRPMODR.
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*/
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void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
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unsigned int reg_val = gicd_read_igrpmodr(base, id);
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gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num));
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}
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/*
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* Accessor to clear the bit corresponding to interrupt ID
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* in GIC Distributor IGRPMODR.
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*/
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void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
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unsigned int reg_val = gicd_read_igrpmodr(base, id);
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gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num));
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}
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/*
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* Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the
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* interrupt `id`, 4 interrupts IDs at a time.
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*/
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unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> IPRIORITYR_SHIFT;
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return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
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}
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/*
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* Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the
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* interrupt `id`, 4 interrupts IDs at a time.
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*/
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void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> IPRIORITYR_SHIFT;
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mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
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}
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/*
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* Accessor to get the bit corresponding to interrupt ID
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* from GIC Re-distributor IGROUPR0.
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*/
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unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
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unsigned int reg_val = gicr_read_igroupr0(base);
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return (reg_val >> bit_num) & 0x1;
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}
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/*
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* Accessor to set the bit corresponding to interrupt ID
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* in GIC Re-distributor IGROUPR0.
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*/
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void gicr_set_igroupr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
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unsigned int reg_val = gicr_read_igroupr0(base);
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gicr_write_igroupr0(base, reg_val | (1 << bit_num));
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}
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/*
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* Accessor to clear the bit corresponding to interrupt ID
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* in GIC Re-distributor IGROUPR0.
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*/
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void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
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unsigned int reg_val = gicr_read_igroupr0(base);
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gicr_write_igroupr0(base, reg_val & ~(1 << bit_num));
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}
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/*
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* Accessor to get the bit corresponding to interrupt ID
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* from GIC Re-distributor IGRPMODR0.
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*/
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unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
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unsigned int reg_val = gicr_read_igrpmodr0(base);
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return (reg_val >> bit_num) & 0x1;
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}
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/*
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* Accessor to set the bit corresponding to interrupt ID
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* in GIC Re-distributor IGRPMODR0.
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*/
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void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
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unsigned int reg_val = gicr_read_igrpmodr0(base);
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gicr_write_igrpmodr0(base, reg_val | (1 << bit_num));
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}
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/*
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* Accessor to clear the bit corresponding to interrupt ID
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* in GIC Re-distributor IGRPMODR0.
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*/
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void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
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unsigned int reg_val = gicr_read_igrpmodr0(base);
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gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num));
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}
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/*
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* Accessor to set the bit corresponding to interrupt ID
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* in GIC Re-distributor ISENABLER0.
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*/
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void gicr_set_isenabler0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
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gicr_write_isenabler0(base, (1 << bit_num));
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}
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/*
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* Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
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* ICENABLER0.
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*/
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void gicr_set_icenabler0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
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gicr_write_icenabler0(base, (1 << bit_num));
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}
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/*
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* Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
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* ISACTIVER0.
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*/
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unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
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unsigned int reg_val = gicr_read_isactiver0(base);
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return (reg_val >> bit_num) & 0x1;
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}
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/*
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* Accessor to clear the bit corresponding to interrupt ID in GIC Re-distributor
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* ICPENDRR0.
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*/
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void gicr_set_icpendr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
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gicr_write_icpendr0(base, (1 << bit_num));
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}
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/*
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* Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
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* ISPENDR0.
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*/
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void gicr_set_ispendr0(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
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gicr_write_ispendr0(base, (1 << bit_num));
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}
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/*
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* Accessor to set the byte corresponding to interrupt ID
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* in GIC Re-distributor IPRIORITYR.
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*/
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void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
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{
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mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK);
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}
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/*
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* Accessor to set the bit fields corresponding to interrupt ID
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* in GIC Re-distributor ICFGR0.
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*/
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void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
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{
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/* Interrupt configuration is a 2-bit field */
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unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
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unsigned int bit_shift = bit_num << 1;
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uint32_t reg_val = gicr_read_icfgr0(base);
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/* Clear the field, and insert required configuration */
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reg_val &= ~(GIC_CFG_MASK << bit_shift);
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reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
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gicr_write_icfgr0(base, reg_val);
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}
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/*
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* Accessor to set the bit fields corresponding to interrupt ID
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* in GIC Re-distributor ICFGR1.
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*/
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void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg)
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{
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/* Interrupt configuration is a 2-bit field */
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unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
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unsigned int bit_shift = bit_num << 1;
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uint32_t reg_val = gicr_read_icfgr1(base);
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/* Clear the field, and insert required configuration */
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reg_val &= ~(GIC_CFG_MASK << bit_shift);
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reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
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gicr_write_icfgr1(base, reg_val);
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}
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/******************************************************************************
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* This function marks the core as awake in the re-distributor and
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* ensures that the interface is active.
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*****************************************************************************/
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void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
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{
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/*
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* The WAKER_PS_BIT should be changed to 0
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* only when WAKER_CA_BIT is 1.
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*/
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assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT);
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/* Mark the connected core as awake */
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gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
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/* Wait till the WAKER_CA_BIT changes to 0 */
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while (gicr_read_waker(gicr_base) & WAKER_CA_BIT)
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;
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}
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/******************************************************************************
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* This function marks the core as asleep in the re-distributor and ensures
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* that the interface is quiescent.
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*****************************************************************************/
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void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
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{
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/* Mark the connected core as asleep */
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gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
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/* Wait till the WAKER_CA_BIT changes to 1 */
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while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT))
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;
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}
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/*******************************************************************************
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* This function probes the Redistributor frames when the driver is initialised
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* and saves their base addresses. These base addresses are used later to
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* initialise each Redistributor interface.
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******************************************************************************/
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void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
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unsigned int rdistif_num,
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uintptr_t gicr_base,
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mpidr_hash_fn mpidr_to_core_pos)
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{
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u_register_t mpidr;
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unsigned int proc_num;
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unsigned long long typer_val;
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uintptr_t rdistif_base = gicr_base;
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assert(rdistif_base_addrs);
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/*
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* Iterate over the Redistributor frames. Store the base address of each
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* frame in the platform provided array. Use the "Processor Number"
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* field to index into the array if the platform has not provided a hash
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* function to convert an MPIDR (obtained from the "Affinity Value"
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* field into a linear index.
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*/
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do {
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typer_val = gicr_read_typer(rdistif_base);
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if (mpidr_to_core_pos) {
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mpidr = mpidr_from_gicr_typer(typer_val);
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proc_num = mpidr_to_core_pos(mpidr);
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} else {
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proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
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TYPER_PROC_NUM_MASK;
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}
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assert(proc_num < rdistif_num);
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rdistif_base_addrs[proc_num] = rdistif_base;
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rdistif_base += (1 << GICR_PCPUBASE_SHIFT);
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} while (!(typer_val & TYPER_LAST_BIT));
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}
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/*******************************************************************************
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* Helper function to configure the default attributes of SPIs.
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******************************************************************************/
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void gicv3_spis_config_defaults(uintptr_t gicd_base)
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{
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unsigned int index, num_ints;
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num_ints = gicd_read_typer(gicd_base);
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num_ints &= TYPER_IT_LINES_NO_MASK;
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num_ints = (num_ints + 1) << 5;
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/*
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* Treat all SPIs as G1NS by default. The number of interrupts is
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* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
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*/
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for (index = MIN_SPI_ID; index < num_ints; index += 32)
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gicd_write_igroupr(gicd_base, index, ~0U);
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/* Setup the default SPI priorities doing four at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 4)
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gicd_write_ipriorityr(gicd_base,
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index,
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GICD_IPRIORITYR_DEF_VAL);
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/*
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* Treat all SPIs as level triggered by default, write 16 at
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* a time
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*/
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for (index = MIN_SPI_ID; index < num_ints; index += 16)
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gicd_write_icfgr(gicd_base, index, 0);
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}
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#if !ERROR_DEPRECATED
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/*******************************************************************************
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* Helper function to configure secure G0 and G1S SPIs.
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******************************************************************************/
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void gicv3_secure_spis_config(uintptr_t gicd_base,
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unsigned int num_ints,
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const unsigned int *sec_intr_list,
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unsigned int int_grp)
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{
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unsigned int index, irq_num;
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unsigned long long gic_affinity_val;
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assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
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/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
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assert(num_ints ? (uintptr_t)sec_intr_list : 1);
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for (index = 0; index < num_ints; index++) {
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irq_num = sec_intr_list[index];
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if (irq_num >= MIN_SPI_ID) {
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/* Configure this interrupt as a secure interrupt */
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gicd_clr_igroupr(gicd_base, irq_num);
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/* Configure this interrupt as G0 or a G1S interrupt */
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if (int_grp == INTR_GROUP1S)
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gicd_set_igrpmodr(gicd_base, irq_num);
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else
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gicd_clr_igrpmodr(gicd_base, irq_num);
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/* Set the priority of this interrupt */
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gicd_set_ipriorityr(gicd_base,
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irq_num,
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GIC_HIGHEST_SEC_PRIORITY);
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/* Target SPIs to the primary CPU */
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gic_affinity_val =
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gicd_irouter_val_from_mpidr(read_mpidr(), 0);
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gicd_write_irouter(gicd_base,
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irq_num,
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gic_affinity_val);
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/* Enable this interrupt */
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gicd_set_isenabler(gicd_base, irq_num);
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}
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}
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}
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#endif
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/*******************************************************************************
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* Helper function to configure properties of secure SPIs
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******************************************************************************/
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unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
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const interrupt_prop_t *interrupt_props,
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unsigned int interrupt_props_num)
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{
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unsigned int i;
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const interrupt_prop_t *current_prop;
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unsigned long long gic_affinity_val;
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unsigned int ctlr_enable = 0;
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/* Make sure there's a valid property array */
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assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
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for (i = 0; i < interrupt_props_num; i++) {
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current_prop = &interrupt_props[i];
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if (current_prop->intr_num < MIN_SPI_ID)
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continue;
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/* Configure this interrupt as a secure interrupt */
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gicd_clr_igroupr(gicd_base, current_prop->intr_num);
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/* Configure this interrupt as G0 or a G1S interrupt */
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assert((current_prop->intr_grp == INTR_GROUP0) ||
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(current_prop->intr_grp == INTR_GROUP1S));
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if (current_prop->intr_grp == INTR_GROUP1S) {
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gicd_set_igrpmodr(gicd_base, current_prop->intr_num);
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ctlr_enable |= CTLR_ENABLE_G1S_BIT;
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} else {
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gicd_clr_igrpmodr(gicd_base, current_prop->intr_num);
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ctlr_enable |= CTLR_ENABLE_G0_BIT;
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}
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/* Set interrupt configuration */
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gicd_set_icfgr(gicd_base, current_prop->intr_num,
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current_prop->intr_cfg);
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/* Set the priority of this interrupt */
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gicd_set_ipriorityr(gicd_base, current_prop->intr_num,
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current_prop->intr_pri);
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/* Target SPIs to the primary CPU */
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gic_affinity_val = gicd_irouter_val_from_mpidr(read_mpidr(), 0);
|
|
gicd_write_irouter(gicd_base, current_prop->intr_num,
|
|
gic_affinity_val);
|
|
|
|
/* Enable this interrupt */
|
|
gicd_set_isenabler(gicd_base, current_prop->intr_num);
|
|
}
|
|
|
|
return ctlr_enable;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Helper function to configure the default attributes of SPIs.
|
|
******************************************************************************/
|
|
void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
|
|
{
|
|
unsigned int index;
|
|
|
|
/*
|
|
* Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
|
|
* more scalable approach as it avoids clearing the enable bits in the
|
|
* GICD_CTLR
|
|
*/
|
|
gicr_write_icenabler0(gicr_base, ~0);
|
|
gicr_wait_for_pending_write(gicr_base);
|
|
|
|
/* Treat all SGIs/PPIs as G1NS by default. */
|
|
gicr_write_igroupr0(gicr_base, ~0U);
|
|
|
|
/* Setup the default PPI/SGI priorities doing four at a time */
|
|
for (index = 0; index < MIN_SPI_ID; index += 4)
|
|
gicr_write_ipriorityr(gicr_base,
|
|
index,
|
|
GICD_IPRIORITYR_DEF_VAL);
|
|
|
|
/* Configure all PPIs as level triggered by default */
|
|
gicr_write_icfgr1(gicr_base, 0);
|
|
}
|
|
|
|
#if !ERROR_DEPRECATED
|
|
/*******************************************************************************
|
|
* Helper function to configure secure G0 and G1S SPIs.
|
|
******************************************************************************/
|
|
void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
|
|
unsigned int num_ints,
|
|
const unsigned int *sec_intr_list,
|
|
unsigned int int_grp)
|
|
{
|
|
unsigned int index, irq_num;
|
|
|
|
assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
|
|
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
|
|
assert(num_ints ? (uintptr_t)sec_intr_list : 1);
|
|
|
|
for (index = 0; index < num_ints; index++) {
|
|
irq_num = sec_intr_list[index];
|
|
if (irq_num < MIN_SPI_ID) {
|
|
|
|
/* Configure this interrupt as a secure interrupt */
|
|
gicr_clr_igroupr0(gicr_base, irq_num);
|
|
|
|
/* Configure this interrupt as G0 or a G1S interrupt */
|
|
if (int_grp == INTR_GROUP1S)
|
|
gicr_set_igrpmodr0(gicr_base, irq_num);
|
|
else
|
|
gicr_clr_igrpmodr0(gicr_base, irq_num);
|
|
|
|
/* Set the priority of this interrupt */
|
|
gicr_set_ipriorityr(gicr_base,
|
|
irq_num,
|
|
GIC_HIGHEST_SEC_PRIORITY);
|
|
|
|
/* Enable this interrupt */
|
|
gicr_set_isenabler0(gicr_base, irq_num);
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*******************************************************************************
|
|
* Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
|
|
******************************************************************************/
|
|
unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
|
|
const interrupt_prop_t *interrupt_props,
|
|
unsigned int interrupt_props_num)
|
|
{
|
|
unsigned int i;
|
|
const interrupt_prop_t *current_prop;
|
|
unsigned int ctlr_enable = 0;
|
|
|
|
/* Make sure there's a valid property array */
|
|
assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
|
|
|
|
for (i = 0; i < interrupt_props_num; i++) {
|
|
current_prop = &interrupt_props[i];
|
|
|
|
if (current_prop->intr_num >= MIN_SPI_ID)
|
|
continue;
|
|
|
|
/* Configure this interrupt as a secure interrupt */
|
|
gicr_clr_igroupr0(gicr_base, current_prop->intr_num);
|
|
|
|
/* Configure this interrupt as G0 or a G1S interrupt */
|
|
assert((current_prop->intr_grp == INTR_GROUP0) ||
|
|
(current_prop->intr_grp == INTR_GROUP1S));
|
|
if (current_prop->intr_grp == INTR_GROUP1S) {
|
|
gicr_set_igrpmodr0(gicr_base, current_prop->intr_num);
|
|
ctlr_enable |= CTLR_ENABLE_G1S_BIT;
|
|
} else {
|
|
gicr_clr_igrpmodr0(gicr_base, current_prop->intr_num);
|
|
ctlr_enable |= CTLR_ENABLE_G0_BIT;
|
|
}
|
|
|
|
/* Set the priority of this interrupt */
|
|
gicr_set_ipriorityr(gicr_base, current_prop->intr_num,
|
|
current_prop->intr_pri);
|
|
|
|
/*
|
|
* Set interrupt configuration for PPIs. Configuration for SGIs
|
|
* are ignored.
|
|
*/
|
|
if ((current_prop->intr_num >= MIN_PPI_ID) &&
|
|
(current_prop->intr_num < MIN_SPI_ID)) {
|
|
gicr_set_icfgr1(gicr_base, current_prop->intr_num,
|
|
current_prop->intr_cfg);
|
|
}
|
|
|
|
/* Enable this interrupt */
|
|
gicr_set_isenabler0(gicr_base, current_prop->intr_num);
|
|
}
|
|
|
|
return ctlr_enable;
|
|
}
|