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https://github.com/ARM-software/arm-trusted-firmware.git
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872be88a29
In order to quantify the overall time spent in the PSCI software implementation, an initial collection of PMF instrumentation points has been added. Instrumentation has been added to the following code paths: - Entry to PSCI SMC handler. The timestamp is captured as early as possible during the runtime exception and stored in memory before entering the PSCI SMC handler. - Exit from PSCI SMC handler. The timestamp is captured after normal return from the PSCI SMC handler or if a low power state was requested it is captured in the bl31 warm boot path before return to normal world. - Entry to low power state. The timestamp is captured before entry to a low power state which implies either standby or power down. As these power states are mutually exclusive, only one timestamp is defined to describe both. It is possible to differentiate between the two power states using the PSCI STAT interface. - Exit from low power state. The timestamp is captured after a standby or power up operation has completed. To calculate the number of cycles spent running code in Trusted Firmware one can perform the following calculation: (exit_psci - enter_psci) - (exit_low_pwr - enter_low_pwr). The resulting number of cycles can be converted to time given the frequency of the counter. Change-Id: Ie3b8f3d16409b6703747093b3a2d5c7429ad0166 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
452 lines
14 KiB
ArmAsm
452 lines
14 KiB
ArmAsm
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <cpu_data.h>
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#include <interrupt_mgmt.h>
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#include <platform_def.h>
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#include <runtime_svc.h>
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.globl runtime_exceptions
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/* -----------------------------------------------------
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* Handle SMC exceptions separately from other sync.
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* exceptions.
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* -----------------------------------------------------
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*/
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.macro handle_sync_exception
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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#if ENABLE_RUNTIME_INSTRUMENTATION
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/*
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* Read the timestamp value and store it in per-cpu data.
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* The value will be extracted from per-cpu data by the
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* C level SMC handler and saved to the PMF timestamp region.
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*/
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mrs x30, cntpct_el0
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str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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mrs x29, tpidr_el3
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str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
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ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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#endif
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_AARCH32_SMC
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b.eq smc_handler32
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cmp x30, #EC_AARCH64_SMC
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b.eq smc_handler64
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/* -----------------------------------------------------
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* The following code handles any synchronous exception
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* that is not an SMC.
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* -----------------------------------------------------
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*/
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bl report_unhandled_exception
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.endm
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/* -----------------------------------------------------
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* This macro handles FIQ or IRQ interrupts i.e. EL3,
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* S-EL1 and NS interrupts.
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* -----------------------------------------------------
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*/
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.macro handle_interrupt_exception label
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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bl save_gp_registers
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/*
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* Save the EL3 system registers needed to return from
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* this exception.
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*/
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mrs x0, spsr_el3
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mrs x1, elr_el3
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stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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/* Switch to the runtime stack i.e. SP_EL0 */
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ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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mov x20, sp
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msr spsel, #0
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mov sp, x2
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/*
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* Find out whether this is a valid interrupt type. If the
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* interrupt controller reports a spurious interrupt then
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* return to where we came from.
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*/
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bl plat_ic_get_pending_interrupt_type
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cmp x0, #INTR_TYPE_INVAL
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b.eq interrupt_exit_\label
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/*
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* Get the registered handler for this interrupt type. A
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* NULL return value could be 'cause of the following
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* conditions:
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*
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* a. An interrupt of a type was routed correctly but a
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* handler for its type was not registered.
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*
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* b. An interrupt of a type was not routed correctly so
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* a handler for its type was not registered.
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*
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* c. An interrupt of a type was routed correctly to EL3,
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* but was deasserted before its pending state could
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* be read. Another interrupt of a different type pended
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* at the same time and its type was reported as pending
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* instead. However, a handler for this type was not
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* registered.
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*
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* a. and b. can only happen due to a programming error.
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* The occurrence of c. could be beyond the control of
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* Trusted Firmware. It makes sense to return from this
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* exception instead of reporting an error.
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*/
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bl get_interrupt_type_handler
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cbz x0, interrupt_exit_\label
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mov x21, x0
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mov x0, #INTR_ID_UNAVAILABLE
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/* Set the current security state in the 'flags' parameter */
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mrs x2, scr_el3
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ubfx x1, x2, #0, #1
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/* Restore the reference to the 'handle' i.e. SP_EL3 */
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mov x2, x20
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/* x3 will point to a cookie (not used now) */
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mov x3, xzr
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/* Call the interrupt type handler */
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blr x21
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interrupt_exit_\label:
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/* Return from exception, possibly in a different security state */
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b el3_exit
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.endm
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.macro save_x18_to_x29_sp_el0
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stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
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stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
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stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
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stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
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stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
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stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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mrs x18, sp_el0
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str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
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.endm
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vector_base runtime_exceptions
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_sp_el0
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/* -----------------------------------------------------
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* We don't expect any synchronous exceptions from EL3
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* -----------------------------------------------------
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*/
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bl report_unhandled_exception
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check_vector_size sync_exception_sp_el0
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/* -----------------------------------------------------
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* EL3 code is non-reentrant. Any asynchronous exception
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* is a serious error. Loop infinitely.
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* -----------------------------------------------------
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*/
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vector_entry irq_sp_el0
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bl report_unhandled_interrupt
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check_vector_size irq_sp_el0
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vector_entry fiq_sp_el0
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bl report_unhandled_interrupt
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check_vector_size fiq_sp_el0
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vector_entry serror_sp_el0
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bl report_unhandled_exception
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check_vector_size serror_sp_el0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_sp_elx
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/* -----------------------------------------------------
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* This exception will trigger if anything went wrong
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* during a previous exception entry or exit or while
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* handling an earlier unexpected synchronous exception.
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* There is a high probability that SP_EL3 is corrupted.
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* -----------------------------------------------------
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*/
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bl report_unhandled_exception
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check_vector_size sync_exception_sp_elx
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vector_entry irq_sp_elx
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bl report_unhandled_interrupt
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check_vector_size irq_sp_elx
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vector_entry fiq_sp_elx
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bl report_unhandled_interrupt
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check_vector_size fiq_sp_elx
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vector_entry serror_sp_elx
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bl report_unhandled_exception
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check_vector_size serror_sp_elx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_aarch64
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/* -----------------------------------------------------
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* This exception vector will be the entry point for
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* SMCs and traps that are unhandled at lower ELs most
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* commonly. SP_EL3 should point to a valid cpu context
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* where the general purpose and system register state
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* can be saved.
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* -----------------------------------------------------
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*/
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handle_sync_exception
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check_vector_size sync_exception_aarch64
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/* -----------------------------------------------------
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* Asynchronous exceptions from lower ELs are not
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* currently supported. Report their occurrence.
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* -----------------------------------------------------
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*/
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vector_entry irq_aarch64
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handle_interrupt_exception irq_aarch64
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check_vector_size irq_aarch64
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vector_entry fiq_aarch64
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handle_interrupt_exception fiq_aarch64
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check_vector_size fiq_aarch64
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vector_entry serror_aarch64
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bl report_unhandled_exception
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check_vector_size serror_aarch64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_aarch32
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/* -----------------------------------------------------
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* This exception vector will be the entry point for
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* SMCs and traps that are unhandled at lower ELs most
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* commonly. SP_EL3 should point to a valid cpu context
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* where the general purpose and system register state
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* can be saved.
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* -----------------------------------------------------
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*/
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handle_sync_exception
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check_vector_size sync_exception_aarch32
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/* -----------------------------------------------------
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* Asynchronous exceptions from lower ELs are not
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* currently supported. Report their occurrence.
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* -----------------------------------------------------
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*/
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vector_entry irq_aarch32
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handle_interrupt_exception irq_aarch32
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check_vector_size irq_aarch32
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vector_entry fiq_aarch32
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handle_interrupt_exception fiq_aarch32
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check_vector_size fiq_aarch32
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vector_entry serror_aarch32
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bl report_unhandled_exception
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check_vector_size serror_aarch32
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/* -----------------------------------------------------
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* The following code handles secure monitor calls.
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* Depending upon the execution state from where the SMC
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* has been invoked, it frees some general purpose
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* registers to perform the remaining tasks. They
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* involve finding the runtime service handler that is
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* the target of the SMC & switching to runtime stacks
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* (SP_EL0) before calling the handler.
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*
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* Note that x30 has been explicitly saved and can be
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* used here
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* -----------------------------------------------------
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*/
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func smc_handler
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smc_handler32:
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/* Check whether aarch32 issued an SMC64 */
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tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
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/* -----------------------------------------------------
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* Since we're are coming from aarch32, x8-x18 need to
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* be saved as per SMC32 calling convention. If a lower
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* EL in aarch64 is making an SMC32 call then it must
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* have saved x8-x17 already therein.
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* -----------------------------------------------------
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*/
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stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
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stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
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stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
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stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
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stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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/* x4-x7, x18, sp_el0 are saved below */
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smc_handler64:
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/* -----------------------------------------------------
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* Populate the parameters for the SMC handler. We
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* already have x0-x4 in place. x5 will point to a
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* cookie (not used now). x6 will point to the context
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* structure (SP_EL3) and x7 will contain flags we need
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* to pass to the handler Hence save x5-x7. Note that x4
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* only needs to be preserved for AArch32 callers but we
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* do it for AArch64 callers as well for convenience
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* -----------------------------------------------------
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*/
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stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
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/* Save rest of the gpregs and sp_el0*/
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save_x18_to_x29_sp_el0
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mov x5, xzr
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mov x6, sp
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/* Get the unique owning entity number */
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ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
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ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
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orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
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adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
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/* Load descriptor index from array of indices */
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adr x14, rt_svc_descs_indices
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ldrb w15, [x14, x16]
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/* -----------------------------------------------------
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* Restore the saved C runtime stack value which will
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* become the new SP_EL0 i.e. EL3 runtime stack. It was
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* saved in the 'cpu_context' structure prior to the last
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* ERET from EL3.
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* -----------------------------------------------------
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*/
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ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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/*
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* Any index greater than 127 is invalid. Check bit 7 for
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* a valid index
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*/
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tbnz w15, 7, smc_unknown
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/* Switch to SP_EL0 */
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msr spsel, #0
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/* -----------------------------------------------------
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* Get the descriptor using the index
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* x11 = (base + off), x15 = index
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*
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* handler = (base + off) + (index << log2(size))
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* -----------------------------------------------------
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*/
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lsl w10, w15, #RT_SVC_SIZE_LOG2
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ldr x15, [x11, w10, uxtw]
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/* -----------------------------------------------------
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* Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
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* is a world switch during SMC handling.
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* TODO: Revisit if all system registers can be saved
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* later.
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* -----------------------------------------------------
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*/
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mrs x16, spsr_el3
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mrs x17, elr_el3
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mrs x18, scr_el3
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stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
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/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
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bfi x7, x18, #0, #1
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mov sp, x12
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/* -----------------------------------------------------
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* Call the Secure Monitor Call handler and then drop
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* directly into el3_exit() which will program any
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* remaining architectural state prior to issuing the
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* ERET to the desired lower EL.
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* -----------------------------------------------------
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*/
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#if DEBUG
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cbz x15, rt_svc_fw_critical_error
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#endif
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blr x15
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b el3_exit
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smc_unknown:
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/*
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* Here we restore x4-x18 regardless of where we came from. AArch32
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* callers will find the registers contents unchanged, but AArch64
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* callers will find the registers modified (with stale earlier NS
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* content). Either way, we aren't leaking any secure information
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* through them
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*/
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mov w0, #SMC_UNK
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b restore_gp_registers_callee_eret
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smc_prohibited:
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mov w0, #SMC_UNK
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eret
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rt_svc_fw_critical_error:
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msr spsel, #1 /* Switch to SP_ELx */
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bl report_unhandled_exception
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endfunc smc_handler
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