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9af07df050
The workaround is added to the Cortex-A55 cpu specific file. The workaround is disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
336 lines
8.2 KiB
ArmAsm
336 lines
8.2 KiB
ArmAsm
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a55.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A55 Errata #768277.
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* This applies only to revision r0p0 of Cortex A55.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a55_768277_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_768277
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cbz x0, 1f
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mrs x1, CORTEX_A55_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
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msr CORTEX_A55_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a55_768277_wa
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func check_errata_768277
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_768277
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/* ------------------------------------------------------------------
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* Errata Workaround for Cortex A55 Errata #778703.
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* This applies only to revision r0p0 of Cortex A55 where L2 cache is
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* not configured.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ------------------------------------------------------------------
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*/
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func errata_a55_778703_wa
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/*
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* Compare x0 against revision r0p0 and check that no private L2 cache
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* is configured
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*/
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mov x17, x30
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bl check_errata_778703
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cbz x0, 1f
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mrs x1, CORTEX_A55_CPUECTLR_EL1
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orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
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msr CORTEX_A55_CPUECTLR_EL1, x1
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mrs x1, CORTEX_A55_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
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msr CORTEX_A55_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a55_778703_wa
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func check_errata_778703
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mov x16, x30
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mov x1, #0x00
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bl cpu_rev_var_ls
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/*
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* Check that no private L2 cache is configured
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*/
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mrs x1, CORTEX_A55_CLIDR_EL1
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and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3
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cmp x1, #0
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mov x2, #ERRATA_NOT_APPLIES
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csel x0, x0, x2, eq
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ret x16
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endfunc check_errata_778703
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/* --------------------------------------------------
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* Errata Workaround for Cortex A55 Errata #798797.
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* This applies only to revision r0p0 of Cortex A55.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a55_798797_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_798797
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cbz x0, 1f
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mrs x1, CORTEX_A55_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
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msr CORTEX_A55_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a55_798797_wa
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func check_errata_798797
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_798797
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/* --------------------------------------------------------------------
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* Errata Workaround for Cortex A55 Errata #846532.
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* This applies only to revisions <= r0p1 of Cortex A55.
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* Disabling dual-issue has a small impact on performance. Disabling a
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* power optimization feature is an alternate workaround with no impact
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* on performance but with an increase in power consumption (see errata
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* notice).
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------------------------
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*/
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func errata_a55_846532_wa
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/*
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* Compare x0 against revision r0p1
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*/
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mov x17, x30
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bl check_errata_846532
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cbz x0, 1f
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mrs x1, CORTEX_A55_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
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msr CORTEX_A55_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a55_846532_wa
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func check_errata_846532
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mov x1, #0x01
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b cpu_rev_var_ls
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endfunc check_errata_846532
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/* -----------------------------------------------------
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* Errata Workaround for Cortex A55 Errata #903758.
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* This applies only to revisions <= r0p1 of Cortex A55.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* -----------------------------------------------------
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*/
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func errata_a55_903758_wa
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/*
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* Compare x0 against revision r0p1
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*/
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mov x17, x30
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bl check_errata_903758
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cbz x0, 1f
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mrs x1, CORTEX_A55_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
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msr CORTEX_A55_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a55_903758_wa
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func check_errata_903758
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mov x1, #0x01
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b cpu_rev_var_ls
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endfunc check_errata_903758
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/* -----------------------------------------------------
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* Errata Workaround for Cortex A55 Errata #1221012.
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* This applies only to revisions <= r1p0 of Cortex A55.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* -----------------------------------------------------
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*/
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func errata_a55_1221012_wa
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/*
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* Compare x0 against revision r1p0
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*/
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mov x17, x30
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bl check_errata_1221012
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cbz x0, 1f
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mov x0, #0x0020
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movk x0, #0x0850, lsl #16
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msr CPUPOR_EL3, x0
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mov x0, #0x0000
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movk x0, #0x1FF0, lsl #16
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movk x0, #0x2, lsl #32
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msr CPUPMR_EL3, x0
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mov x0, #0x03fd
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movk x0, #0x0110, lsl #16
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msr CPUPCR_EL3, x0
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mov x0, #0x1
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msr CPUPSELR_EL3, x0
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mov x0, #0x0040
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movk x0, #0x08D0, lsl #16
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msr CPUPOR_EL3, x0
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mov x0, #0x0040
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movk x0, #0x1FF0, lsl #16
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movk x0, #0x2, lsl #32
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msr CPUPMR_EL3, x0
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mov x0, #0x03fd
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movk x0, #0x0110, lsl #16
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msr CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_a55_1221012_wa
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func check_errata_1221012
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1221012
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func cortex_a55_reset_func
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mov x19, x30
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#if ERRATA_DSU_798953
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bl errata_dsu_798953_wa
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#endif
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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#endif
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A55_768277
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mov x0, x18
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bl errata_a55_768277_wa
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#endif
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#if ERRATA_A55_778703
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mov x0, x18
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bl errata_a55_778703_wa
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#endif
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#if ERRATA_A55_798797
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mov x0, x18
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bl errata_a55_798797_wa
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#endif
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#if ERRATA_A55_846532
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mov x0, x18
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bl errata_a55_846532_wa
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#endif
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#if ERRATA_A55_903758
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mov x0, x18
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bl errata_a55_903758_wa
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#endif
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#if ERRATA_A55_1221012
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mov x0, x18
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bl errata_a55_1221012_wa
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#endif
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ret x19
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endfunc cortex_a55_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a55_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A55_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK
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msr CORTEX_A55_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a55_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
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*/
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func cortex_a55_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision variant information is at x8, where
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* "report_errata" is expecting it and it doesn't corrupt it.
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*/
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report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953
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report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
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report_errata ERRATA_A55_768277, cortex_a55, 768277
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report_errata ERRATA_A55_778703, cortex_a55, 778703
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report_errata ERRATA_A55_798797, cortex_a55, 798797
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report_errata ERRATA_A55_846532, cortex_a55, 846532
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report_errata ERRATA_A55_903758, cortex_a55, 903758
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report_errata ERRATA_A55_1221012, cortex_a55, 1221012
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a55_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a55 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a55_regs, "aS"
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cortex_a55_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a55_cpu_reg_dump
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adr x6, cortex_a55_regs
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mrs x8, CORTEX_A55_CPUECTLR_EL1
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ret
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endfunc cortex_a55_cpu_reg_dump
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declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \
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cortex_a55_reset_func, \
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cortex_a55_core_pwr_dwn
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