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83ec7e452c
The current code is incredibly resilient to updates to the spec and has worked quite well so far. However, recent implementations expose a weakness in that this is rather slow. A large part of it is written in assembly, making it opaque to the compiler for optimisations. The future proofness requires reading registers that are effectively `volatile`, making it even harder for the compiler, as well as adding lots of implicit barriers, making it hard for the microarchitecutre to optimise as well. We can make a few assumptions, checked by a few well placed asserts, and remove a lot of this burden. For a start, at the moment there are 4 group 0 counters with static assignments. Contexting them is a trivial affair that doesn't need a loop. Similarly, there can only be up to 16 group 1 counters. Contexting them is a bit harder, but we can do with a single branch with a falling through switch. If/when both of these change, we have a pair of asserts and the feature detection mechanism to guard us against pretending that we support something we don't. We can drop contexting of the offset registers. They are fully accessible by EL2 and as such are its responsibility to preserve on powerdown. Another small thing we can do, is pass the core_pos into the hook. The caller already knows which core we're running on, we don't need to call this non-trivial function again. Finally, knowing this, we don't really need the auxiliary AMUs to be described by the device tree. Linux doesn't care at the moment, and any information we need for EL3 can be neatly placed in a simple array. All of this, combined with lifting the actual saving out of assembly, reduces the instructions to save the context from 180 to 40, including a lot fewer branches. The code is also much shorter and easier to read. Also propagate to aarch32 so that the two don't diverge too much. Change-Id: Ib62e6e9ba5be7fb9fb8965c8eee148d5598a5361 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
103 lines
3.4 KiB
C
103 lines
3.4 KiB
C
/*
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* Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CONTEXT_MGMT_H
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#define CONTEXT_MGMT_H
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#include <assert.h>
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#include <context.h>
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#include <stdint.h>
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#include <arch.h>
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/*******************************************************************************
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* Forward declarations
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******************************************************************************/
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struct entry_point_info;
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/*******************************************************************************
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* Function & variable prototypes
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******************************************************************************/
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void cm_init(void);
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void *cm_get_context_by_index(unsigned int cpu_idx,
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unsigned int security_state);
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void cm_set_context_by_index(unsigned int cpu_idx,
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void *context,
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unsigned int security_state);
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void *cm_get_context(uint32_t security_state);
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void cm_set_context(void *context, uint32_t security_state);
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void cm_init_my_context(const struct entry_point_info *ep);
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void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep);
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void cm_prepare_el3_exit(uint32_t security_state);
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void cm_prepare_el3_exit_ns(void);
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#if !IMAGE_BL1
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void cm_init_context_by_index(unsigned int cpu_idx,
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const struct entry_point_info *ep);
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#endif /* !IMAGE_BL1 */
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#ifdef __aarch64__
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#if IMAGE_BL31
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void cm_manage_extensions_el3(unsigned int my_idx);
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void manage_extensions_nonsecure_per_world(void);
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void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx);
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void cm_handle_asymmetric_features(void);
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#endif
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#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
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void cm_el2_sysregs_context_save(uint32_t security_state);
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void cm_el2_sysregs_context_restore(uint32_t security_state);
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#else
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void cm_el1_sysregs_context_save(uint32_t security_state);
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void cm_el1_sysregs_context_restore(uint32_t security_state);
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#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
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void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
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void cm_set_elr_spsr_el3(uint32_t security_state,
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uintptr_t entrypoint, uint32_t spsr);
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void cm_write_scr_el3_bit(uint32_t security_state,
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uint32_t bit_pos,
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uint32_t value);
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void cm_set_next_eret_context(uint32_t security_state);
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u_register_t cm_get_scr_el3(uint32_t security_state);
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/* Inline definitions */
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/*******************************************************************************
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* This function is used to program the context that's used for exception
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* return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
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* the required security state
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******************************************************************************/
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static inline void cm_set_next_context(void *context)
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{
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#if ENABLE_ASSERTIONS
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uint64_t sp_mode;
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/*
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* Check that this function is called with SP_EL0 as the stack
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* pointer
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*/
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__asm__ volatile("mrs %0, SPSel\n"
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: "=r" (sp_mode));
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assert(sp_mode == MODE_SP_EL0);
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#endif /* ENABLE_ASSERTIONS */
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__asm__ volatile("msr spsel, #1\n"
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"mov sp, %0\n"
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"msr spsel, #0\n"
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: : "r" (context));
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}
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#else
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void *cm_get_next_context(void);
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void cm_set_next_context(void *context);
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static inline void cm_manage_extensions_el3(unsigned int cpu_idx) {}
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static inline void manage_extensions_nonsecure_per_world(void) {}
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static inline void cm_handle_asymmetric_features(void) {}
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#endif /* __aarch64__ */
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#endif /* CONTEXT_MGMT_H */
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