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27749653c7
Use the same format in all files 's/Copyright (C)/Copyright (c)/g'. Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7 Signed-off-by: Michal Simek <michal.simek@amd.com>
85 lines
1.7 KiB
C
85 lines
1.7 KiB
C
/*
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* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Versal NET IPI agent registers access management
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*/
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#include <errno.h>
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#include <string.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <ipi.h>
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#include <plat_ipi.h>
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#include <plat_private.h>
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/* versal_net ipi configuration table */
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static const struct ipi_config versal_net_ipi_table[IPI_ID_MAX] = {
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/* A72 IPI */
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[IPI_ID_APU] = {
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.ipi_bit_mask = IPI0_TRIG_BIT,
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.ipi_reg_base = IPI0_REG_BASE,
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.secure_only = 0,
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},
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/* PMC IPI */
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[IPI_ID_PMC] = {
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.ipi_bit_mask = PMC_IPI_TRIG_BIT,
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.ipi_reg_base = IPI0_REG_BASE,
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.secure_only = 0,
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},
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/* RPU0 IPI */
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[IPI_ID_RPU0] = {
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.ipi_bit_mask = IPI1_TRIG_BIT,
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.ipi_reg_base = IPI1_REG_BASE,
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.secure_only = 0,
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},
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/* RPU1 IPI */
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[IPI_ID_RPU1] = {
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.ipi_bit_mask = IPI2_TRIG_BIT,
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.ipi_reg_base = IPI2_REG_BASE,
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.secure_only = 0,
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},
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/* IPI3 IPI */
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[IPI_ID_3] = {
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.ipi_bit_mask = IPI3_TRIG_BIT,
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.ipi_reg_base = IPI3_REG_BASE,
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.secure_only = 0,
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},
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/* IPI4 IPI */
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[IPI_ID_4] = {
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.ipi_bit_mask = IPI4_TRIG_BIT,
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.ipi_reg_base = IPI4_REG_BASE,
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.secure_only = 0,
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},
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/* IPI5 IPI */
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[IPI_ID_5] = {
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.ipi_bit_mask = IPI5_TRIG_BIT,
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.ipi_reg_base = IPI5_REG_BASE,
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.secure_only = 0,
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},
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};
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/* versal_net_ipi_config_table_init() - Initialize versal_net IPI configuration data
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*
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* @ipi_config_table - IPI configuration table
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* @ipi_total - Total number of IPI available
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*
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*/
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void versal_net_ipi_config_table_init(void)
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{
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ipi_config_table_init(versal_net_ipi_table, ARRAY_SIZE(versal_net_ipi_table));
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}
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