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https://github.com/ARM-software/arm-trusted-firmware.git
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831b0e9824
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
155 lines
4.7 KiB
ArmAsm
155 lines
4.7 KiB
ArmAsm
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#define K3_BOOT_REASON_COLD_RESET 0x1
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/* ------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint(void)
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* ------------------------------------------------------------------
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*
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* This function is called with the called with the MMU and caches
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* disabled (SCTLR_EL3.M = 0 and SCTLR_EL3.C = 0). The function is
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* responsible for distinguishing between a warm and cold reset for the
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* current CPU using platform-specific means. If it's a warm reset,
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* then it returns the warm reset entrypoint point provided to
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* plat_setup_psci_ops() during BL31 initialization. If it's a cold
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* reset then this function must return zero.
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*
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* This function does not follow the Procedure Call Standard used by
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* the Application Binary Interface for the ARM 64-bit architecture.
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* The caller should not assume that callee saved registers are
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* preserved across a call to this function.
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*/
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.globl plat_get_my_entrypoint
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func plat_get_my_entrypoint
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ldr x0, k3_boot_reason_data_store
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cmp x0, #K3_BOOT_REASON_COLD_RESET
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/* We ONLY support cold boot at this point */
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bne plat_unsupported_boot
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mov x0, #0
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ret
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/*
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* We self manage our boot reason.
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* At load time, we have just a default reason - which is cold reset
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*/
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k3_boot_reason_data_store:
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.word K3_BOOT_REASON_COLD_RESET
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plat_unsupported_boot:
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b plat_unsupported_boot
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endfunc plat_get_my_entrypoint
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/* ------------------------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* ------------------------------------------------------------------
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*
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* This function returns the index of the calling CPU which is used as a
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* CPU-specific linear index into blocks of memory (for example while
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* allocating per-CPU stacks). This function will be invoked very early
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* in the initialization sequence which mandates that this function
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* should be implemented in assembly and should not rely on the
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* avalability of a C runtime environment. This function can clobber x0
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* - x8 and must preserve x9 - x29.
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*
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* This function plays a crucial role in the power domain topology
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* framework in PSCI and details of this can be found in Power Domain
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* Topology Design.
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*/
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.globl plat_my_core_pos
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func plat_my_core_pos
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mrs x0, MPIDR_EL1
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and x1, x0, #MPIDR_CLUSTER_MASK
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lsr x1, x1, #MPIDR_AFF1_SHIFT
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and x0, x0, #MPIDR_CPU_MASK
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cmp x1, 0
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b.eq out
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add x0, x0, #K3_CLUSTER0_CORE_COUNT
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cmp x1, 1
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b.eq out
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add x0, x0, #K3_CLUSTER1_CORE_COUNT
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cmp x1, 2
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b.eq out
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add x0, x0, #K3_CLUSTER2_CORE_COUNT
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out:
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ret
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endfunc plat_my_core_pos
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/* --------------------------------------------------------------------
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* This handler does the following:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
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* --------------------------------------------------------------------
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*/
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.globl plat_reset_handler
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func plat_reset_handler
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/* Only on Cortex-A72 */
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jump_if_cpu_midr CORTEX_A72_MIDR, a72
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ret
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/* Cortex-A72 specific settings */
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a72:
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mrs x0, CORTEX_A72_L2CTLR_EL1
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orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
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msr CORTEX_A72_L2CTLR_EL1, x0
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isb
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ret
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endfunc plat_reset_handler
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0 - x4
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* ---------------------------------------------
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*/
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.globl plat_crash_console_init
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func plat_crash_console_init
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mov_imm x0, CRASH_CONSOLE_BASE
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mov_imm x1, CRASH_CONSOLE_CLK
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mov_imm x2, CRASH_CONSOLE_BAUD_RATE
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mov w3, #0x0
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b console_16550_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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.globl plat_crash_console_putc
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func plat_crash_console_putc
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mov_imm x1, CRASH_CONSOLE_BASE
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b console_16550_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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.globl plat_crash_console_flush
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func plat_crash_console_flush
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mov_imm x0, CRASH_CONSOLE_BASE
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b console_16550_core_flush
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endfunc plat_crash_console_flush
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