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831b0e9824
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
251 lines
6.3 KiB
ArmAsm
251 lines
6.3 KiB
ArmAsm
/*
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* Copyright (c) 2020, ARM Limited. All rights reserved.
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <asm_macros.S>
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#include <cortex_a72.h>
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#ifndef PLAT_a3700
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#include <drivers/marvell/ccu.h>
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#include <drivers/marvell/cache_llc.h>
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#endif
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#include <marvell_def.h>
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#include <platform_def.h>
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.weak plat_marvell_calc_core_pos
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.weak plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl disable_mmu_dcache
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.globl invalidate_tlb_all
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.globl platform_unmap_sram
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.globl disable_sram
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.globl disable_icache
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.globl invalidate_icache_all
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.globl marvell_exit_bootrom
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.globl ca72_l2_enable_unique_clean
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_marvell_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_marvell_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_marvell_calc_core_pos(uint64_t mpidr)
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* Helper function to calculate the core position.
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* With this function: CorePos = (ClusterId * 2) +
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* CoreId
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* -----------------------------------------------------
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*/
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func plat_marvell_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #7
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ret
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endfunc plat_marvell_calc_core_pos
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
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mov_imm x1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ
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mov_imm x2, MARVELL_CONSOLE_BAUDRATE
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#ifdef PLAT_a3700
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b console_a3700_core_init
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#else
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b console_16550_core_init
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#endif
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_MARVELL_CRASH_UART_BASE
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#ifdef PLAT_a3700
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b console_a3700_core_putc
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#else
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b console_16550_core_putc
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#endif
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : r0
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
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#ifdef PLAT_a3700
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b console_a3700_core_flush
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#else
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b console_16550_core_flush
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#endif
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endfunc plat_crash_console_flush
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on ARM
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* platforms. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* -----------------------------------------------------
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* Disable icache, dcache, and MMU
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* -----------------------------------------------------
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*/
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func disable_mmu_dcache
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mrs x0, sctlr_el3
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bic x0, x0, 0x1 /* M bit - MMU */
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bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */
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msr sctlr_el3, x0
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isb
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b mmu_off
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mmu_off:
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ret
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endfunc disable_mmu_dcache
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/* -----------------------------------------------------
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* Disable all TLB entries
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* -----------------------------------------------------
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*/
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func invalidate_tlb_all
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tlbi alle3
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dsb sy
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isb
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ret
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endfunc invalidate_tlb_all
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/* -----------------------------------------------------
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* Disable the i cache
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* -----------------------------------------------------
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*/
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func disable_icache
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mrs x0, sctlr_el3
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bic x0, x0, 0x1000 /* I bit - Icache L1 & L2 */
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msr sctlr_el3, x0
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isb
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ret
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endfunc disable_icache
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/* -----------------------------------------------------
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* Disable all of the i caches
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* -----------------------------------------------------
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*/
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func invalidate_icache_all
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ic ialluis
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isb sy
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ret
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endfunc invalidate_icache_all
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/* -----------------------------------------------------
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* Clear the SRAM enabling bit to unmap SRAM
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* -----------------------------------------------------
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*/
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func platform_unmap_sram
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ldr x0, =CCU_SRAM_WIN_CR
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str wzr, [x0]
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ret
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endfunc platform_unmap_sram
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/* -----------------------------------------------------
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* Disable the SRAM
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* -----------------------------------------------------
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*/
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func disable_sram
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/* Disable the line lockings. They must be disabled expictly
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* or the OS will have problems using the cache */
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ldr x1, =MASTER_LLC_TC0_LOCK
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str wzr, [x1]
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/* Invalidate all ways */
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ldr w1, =LLC_WAY_MASK
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ldr x0, =MASTER_LLC_INV_WAY
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str w1, [x0]
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/* Finally disable LLC */
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ldr x0, =MASTER_LLC_CTRL
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str wzr, [x0]
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ret
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endfunc disable_sram
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/* -----------------------------------------------------
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* Operation when exit bootROM:
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* Disable the MMU
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* Disable and invalidate the dcache
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* Unmap and disable the SRAM
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* Disable and invalidate the icache
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* -----------------------------------------------------
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*/
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func marvell_exit_bootrom
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/* Save the system restore address */
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mov x28, x0
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/* Close the caches and MMU */
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bl disable_mmu_dcache
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/*
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* There is nothing important in the caches now,
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* so invalidate them instead of cleaning.
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*/
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adr x0, __RW_START__
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adr x1, __RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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bl invalidate_tlb_all
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/*
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* Clean the memory mapping of SRAM
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* the DDR mapping will remain to enable boot image to execute
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*/
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bl platform_unmap_sram
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/* Disable the SRAM */
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bl disable_sram
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/* Disable and invalidate icache */
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bl disable_icache
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bl invalidate_icache_all
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mov x0, x28
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br x0
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endfunc marvell_exit_bootrom
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/*
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* Enable L2 UniqueClean evictions with data
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*/
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func ca72_l2_enable_unique_clean
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mrs x0, CORTEX_A72_L2ACTLR_EL1
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orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
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msr CORTEX_A72_L2ACTLR_EL1, x0
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ret
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endfunc ca72_l2_enable_unique_clean
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