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9b2510b69d
This patch applies CVE-2022-23960 workarounds for Cortex-A75, Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3 is implemented for A57/A72 because some revisions are affected by both CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c
20 lines
544 B
C
20 lines
544 B
C
/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_ARCH_SVC_H
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#define ARM_ARCH_SVC_H
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#define SMCCC_VERSION U(0x80000000)
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#define SMCCC_ARCH_FEATURES U(0x80000001)
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#define SMCCC_ARCH_SOC_ID U(0x80000002)
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#define SMCCC_ARCH_WORKAROUND_1 U(0x80008000)
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#define SMCCC_ARCH_WORKAROUND_2 U(0x80007FFF)
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#define SMCCC_ARCH_WORKAROUND_3 U(0x80003FFF)
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#define SMCCC_GET_SOC_VERSION U(0)
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#define SMCCC_GET_SOC_REVISION U(1)
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#endif /* ARM_ARCH_SVC_H */
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