mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
7e532c4bf7
Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
87 lines
2.3 KiB
ArmAsm
87 lines
2.3 KiB
ArmAsm
/*
|
|
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <cci.h>
|
|
#include <gic_common.h>
|
|
#include <gicv2.h>
|
|
#include "rcar_def.h"
|
|
|
|
.section .rodata.gic_reg_name, "aS"
|
|
gicc_regs:
|
|
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
|
|
gicd_pend_reg:
|
|
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
|
|
newline:
|
|
.asciz "\n"
|
|
spacer:
|
|
.asciz ":\t\t0x"
|
|
|
|
/* ---------------------------------------------
|
|
* The below macro prints out relevant GIC
|
|
* registers whenever an unhandled exception is
|
|
* taken in BL3-1.
|
|
* Clobbers: x0 - x10, x16, x17, sp
|
|
* ---------------------------------------------
|
|
*/
|
|
.macro plat_print_gic_regs
|
|
mov_imm x17, RCAR_GICC_BASE
|
|
mov_imm x16, RCAR_GICD_BASE
|
|
print_gicc_regs:
|
|
/* gicc base address is now in x17 */
|
|
adr x6, gicc_regs /* Load the gicc reg list to x6 */
|
|
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
|
|
ldr w8, [x17, #GICC_HPPIR]
|
|
ldr w9, [x17, #GICC_AHPPIR]
|
|
ldr w10, [x17, #GICC_CTLR]
|
|
/* Store to the crash buf and print to console */
|
|
bl str_in_crash_buf_print
|
|
|
|
/* Print the GICD_ISPENDR regs */
|
|
add x7, x16, #GICD_ISPENDR
|
|
adr x4, gicd_pend_reg
|
|
bl asm_print_str
|
|
gicd_ispendr_loop:
|
|
sub x4, x7, x16
|
|
cmp x4, #0x280
|
|
b.eq exit_print_gic_regs
|
|
bl asm_print_hex
|
|
adr x4, spacer
|
|
bl asm_print_str
|
|
ldr x4, [x7], #8
|
|
bl asm_print_hex
|
|
adr x4, newline
|
|
bl asm_print_str
|
|
b gicd_ispendr_loop
|
|
exit_print_gic_regs:
|
|
.endm
|
|
|
|
.section .rodata.cci_reg_name, "aS"
|
|
cci_iface_regs:
|
|
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
|
|
|
|
/* ------------------------------------------------
|
|
* The below macro prints out relevant interconnect
|
|
* registers whenever an unhandled exception is
|
|
* taken in BL3-1.
|
|
* Clobbers: x0 - x9, sp
|
|
* ------------------------------------------------
|
|
*/
|
|
.macro plat_print_interconnect_regs
|
|
adr x6, cci_iface_regs
|
|
/* Store in x7 the base address of the first interface */
|
|
mov_imm x7, (CCI500_BASE + SLAVE_IFACE3_OFFSET)
|
|
ldr w8, [x7, #SNOOP_CTRL_REG]
|
|
/* Store in x7 the base address of the second interface */
|
|
mov_imm x7, (CCI500_BASE + SLAVE_IFACE4_OFFSET)
|
|
ldr w9, [x7, #SNOOP_CTRL_REG]
|
|
/* Store to the crash buf and print to console */
|
|
bl str_in_crash_buf_print
|
|
.endm
|
|
|
|
.macro plat_crash_print_regs
|
|
plat_print_gic_regs
|
|
plat_print_interconnect_regs
|
|
.endm
|