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7e3273e8e4
DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable clock gating of the SCLK domain. This will increase the idle power consumption. This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2. SDEN can be found here: https://developer.arm.com/documentation/SDEN1781796/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I54d948b23e8e01aaf1898ed9fe4e2255dd209318 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
385 lines
9.8 KiB
ArmAsm
385 lines
9.8 KiB
ArmAsm
/*
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* Copyright (c) 2022, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a510.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #1922240.
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* This applies only to revision r0p0 (fixed in r0p1)
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_1922240_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1922240
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cbz x0, 1f
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/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
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mrs x0, CORTEX_A510_CMPXACTLR_EL1
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mov x1, #3
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bfi x0, x1, #10, #2
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msr CORTEX_A510_CMPXACTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_1922240_wa
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func check_errata_1922240
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/* Applies to r0p0 only */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_1922240
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2288014.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0. (fixed in r1p1)
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2288014_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2288014
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cbz x0, 1f
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/* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
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mrs x0, CORTEX_A510_CPUACTLR_EL1
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mov x1, #1
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bfi x0, x1, #18, #1
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msr CORTEX_A510_CPUACTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2288014_wa
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func check_errata_2288014
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/* Applies to r1p0 and below */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2288014
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2042739.
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* This applies only to revisions r0p0, r0p1 and r0p2.
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* (fixed in r0p3)
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2042739_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2042739
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cbz x0, 1f
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/* Apply the workaround by disabling ReadPreferUnique. */
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mrs x0, CORTEX_A510_CPUECTLR_EL1
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mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
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msr CORTEX_A510_CPUECTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2042739_wa
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func check_errata_2042739
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/* Applies to revisions r0p0 - r0p2 */
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mov x1, #0x02
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b cpu_rev_var_ls
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endfunc check_errata_2042739
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2041909.
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* This applies only to revision r0p2 and it is fixed in
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* r0p3. The issue is also present in r0p0 and r0p1 but
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* there is no workaround in those revisions.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x2, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2041909_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2041909
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cbz x0, 1f
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/* Apply workaround */
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mov x0, xzr
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msr S3_6_C15_C4_0, x0
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isb
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mov x0, #0x8500000
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msr S3_6_C15_C4_2, x0
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mov x0, #0x1F700000
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movk x0, #0x8, lsl #32
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msr S3_6_C15_C4_3, x0
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mov x0, #0x3F1
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movk x0, #0x110, lsl #16
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msr S3_6_C15_C4_1, x0
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isb
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1:
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ret x17
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endfunc errata_cortex_a510_2041909_wa
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func check_errata_2041909
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/* Applies only to revision r0p2 */
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mov x1, #0x02
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mov x2, #0x02
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b cpu_rev_var_range
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endfunc check_errata_2041909
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2250311.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0, and is fixed in r1p1.
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* This workaround is not a typical errata fix. MPMM
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* is disabled here, but this conflicts with the BL31
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* MPMM support. So in addition to simply disabling
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* the feature, a flag is set in the MPMM library
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* indicating that it should not be enabled even if
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* ENABLE_MPMM=1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2250311_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2250311
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cbz x0, 1f
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/* Disable MPMM */
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mrs x0, CPUMPMMCR_EL3
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bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
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msr CPUMPMMCR_EL3, x0
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#if ENABLE_MPMM && IMAGE_BL31
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/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
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bl mpmm_errata_disable
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#endif
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1:
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ret x17
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endfunc errata_cortex_a510_2250311_wa
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func check_errata_2250311
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/* Applies to r1p0 and lower */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2250311
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2218950.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0, and is fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2218950_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2218950
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cbz x0, 1f
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/* Source register for BFI */
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mov x1, #1
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/* Set bit 18 in CPUACTLR_EL1 */
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mrs x0, CORTEX_A510_CPUACTLR_EL1
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bfi x0, x1, #18, #1
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msr CORTEX_A510_CPUACTLR_EL1, x0
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/* Set bit 25 in CMPXACTLR_EL1 */
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mrs x0, CORTEX_A510_CMPXACTLR_EL1
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bfi x0, x1, #25, #1
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msr CORTEX_A510_CMPXACTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2218950_wa
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func check_errata_2218950
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/* Applies to r1p0 and lower */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2218950
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2172148.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0, and is fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2172148_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2172148
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cbz x0, 1f
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/*
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* Force L2 allocation of transient lines by setting
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* CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
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*/
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mrs x0, CORTEX_A510_CPUECTLR_EL1
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mov x1, #1
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
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msr CORTEX_A510_CPUECTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2172148_wa
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func check_errata_2172148
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/* Applies to r1p0 and lower */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2172148
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a510_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A510_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a510_core_pwr_dwn
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/*
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* Errata printing function for Cortex-A510. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_a510_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A510_1922240, cortex_a510, 1922240
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report_errata ERRATA_A510_2288014, cortex_a510, 2288014
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report_errata ERRATA_A510_2042739, cortex_a510, 2042739
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report_errata ERRATA_A510_2041909, cortex_a510, 2041909
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report_errata ERRATA_A510_2250311, cortex_a510, 2250311
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report_errata ERRATA_A510_2218950, cortex_a510, 2218950
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report_errata ERRATA_A510_2172148, cortex_a510, 2172148
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report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a510_errata_report
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#endif
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func cortex_a510_reset_func
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mov x19, x30
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/* Disable speculative loads */
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msr SSBS, xzr
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/* Get the CPU revision and stash it in x18. */
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_DSU_2313941
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bl errata_dsu_2313941_wa
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#endif
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#if ERRATA_A510_1922240
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mov x0, x18
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bl errata_cortex_a510_1922240_wa
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#endif
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#if ERRATA_A510_2288014
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mov x0, x18
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bl errata_cortex_a510_2288014_wa
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#endif
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#if ERRATA_A510_2042739
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mov x0, x18
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bl errata_cortex_a510_2042739_wa
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#endif
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#if ERRATA_A510_2041909
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mov x0, x18
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bl errata_cortex_a510_2041909_wa
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#endif
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#if ERRATA_A510_2250311
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mov x0, x18
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bl errata_cortex_a510_2250311_wa
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#endif
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#if ERRATA_A510_2218950
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mov x0, x18
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bl errata_cortex_a510_2218950_wa
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#endif
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#if ERRATA_A510_2172148
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mov x0, x18
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bl errata_cortex_a510_2172148_wa
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#endif
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isb
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ret x19
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endfunc cortex_a510_reset_func
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/* ---------------------------------------------
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* This function provides Cortex-A510 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a510_regs, "aS"
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cortex_a510_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a510_cpu_reg_dump
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adr x6, cortex_a510_regs
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mrs x8, CORTEX_A510_CPUECTLR_EL1
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ret
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endfunc cortex_a510_cpu_reg_dump
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declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \
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cortex_a510_reset_func, \
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cortex_a510_core_pwr_dwn
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