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7e3273e8e4
DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable clock gating of the SCLK domain. This will increase the idle power consumption. This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2. SDEN can be found here: https://developer.arm.com/documentation/SDEN1781796/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I54d948b23e8e01aaf1898ed9fe4e2255dd209318 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
/*
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* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DSU_DEF_H
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#define DSU_DEF_H
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#include <lib/utils_def.h>
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/********************************************************************
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* DSU Cluster Configuration registers definitions
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********************************************************************/
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#define CLUSTERCFR_EL1 S3_0_C15_C3_0
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#define CLUSTERCFR_ACP_SHIFT U(11)
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/********************************************************************
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* DSU Cluster Main Revision ID registers definitions
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********************************************************************/
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#define CLUSTERIDR_EL1 S3_0_C15_C3_1
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#define CLUSTERIDR_REV_SHIFT U(0)
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#define CLUSTERIDR_REV_BITS U(4)
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#define CLUSTERIDR_VAR_SHIFT U(4)
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#define CLUSTERIDR_VAR_BITS U(4)
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/********************************************************************
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* DSU Cluster Auxiliary Control registers definitions
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********************************************************************/
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#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
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#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
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#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
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/********************************************************************
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* Masks applied for DSU errata workarounds
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********************************************************************/
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#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
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#endif /* DSU_DEF_H */
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