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https://github.com/ARM-software/arm-trusted-firmware.git
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7c5eedca4c
JR1, JR2 and JR3 are available for use by the non secure world. Setup the A35 core DID for these job rings. Signed-off-by: Varun Sethi <v.sethi@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: If64d4ce11ebff49a2405d8b561b344fcd7b2614f
94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/*
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* Copyright 2021-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLATFORM_STACK_SIZE 0x400
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#define CACHE_WRITEBACK_GRANULE 64
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#define PLAT_PRIMARY_CPU 0x0
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#define PLATFORM_MAX_CPU_PER_CLUSTER 2
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CORE_COUNT 2
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#define PLATFORM_CLUSTER0_CORE_COUNT 2
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define IMX_PWR_LVL0 MPIDR_AFFLVL0
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#define IMX_PWR_LVL1 MPIDR_AFFLVL1
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#define IMX_PWR_LVL2 MPIDR_AFFLVL2
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#define PWR_DOMAIN_AT_MAX_LVL U(1)
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_OFF_STATE U(4)
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#define PLAT_MAX_RET_STATE U(2)
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#define PLAT_WAIT_RET_STATE U(1)
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#define PLAT_STOP_OFF_STATE U(3)
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#define BL31_BASE 0x20040000
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#define BL31_LIMIT 0x20070000
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 8
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#define MAX_MMAP_REGIONS 9
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#define PLAT_GICD_BASE U(0x2d400000)
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#define PLAT_GICR_BASE U(0x2d440000)
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#define DEVICE0_BASE U(0x20000000)
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#define DEVICE0_SIZE U(0x10000000)
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#define DEVICE1_BASE U(0x30000000)
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#define DEVICE1_SIZE U(0x10000000)
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#define IMX_LPUART4_BASE U(0x29390000)
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#define IMX_LPUART5_BASE U(0x293a0000)
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#define IMX_LPUART_BASE IMX_LPUART5_BASE
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#define IMX_CAAM_BASE U(0x292e0000)
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#define IMX_BOOT_UART_CLK_IN_HZ 24000000
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#define IMX_CONSOLE_BAUDRATE 115200
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#define IMX_CGC1_BASE U(0x292c0000)
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#define IMX_PCC3_BASE U(0x292d0000)
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#define IMX_PCC4_BASE U(0x29800000)
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#define IMX_SIM2_BASE U(0x2da50000)
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#define IMX_CGC2_BASE U(0x2da60000)
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#define IMX_PCC5_BASE U(0x2da70000)
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#define IMX_CMC1_BASE U(0x29240000)
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#define IMX_SIM1_BASE U(0x29290000)
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#define IMX_WDOG3_BASE U(0x292a0000)
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#define IMX_GPIOE_BASE U(0x2D000000)
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#define IMX_GPIOD_BASE U(0x2E200000)
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#define IMX_GPIOF_BASE U(0x2D010000)
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#define SRAM0_BASE U(0x2201F000)
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#define IMX_ROM_ENTRY U(0x1000)
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#define COUNTER_FREQUENCY 1000000
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#define PLAT_NS_IMAGE_OFFSET 0x80200000
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#define BL31_NOBITS_BASE 0x20058000
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#define BL31_NOBITS_LIMIT 0x2006d000
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#define BL31_RWDATA_BASE 0x2006d000
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#define BL31_RWDATA_LIMIT 0x20070000
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/* system memory map define */
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#define DEVICE0_MAP MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW)
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#define DEVICE1_MAP MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW)
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/* MU and FSB */
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#define ELE_MAP MAP_REGION_FLAT(0x27010000, 0x20000, MT_DEVICE | MT_RW | MT_NS)
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#define SEC_SIM_MAP MAP_REGION_FLAT(0x2802B000, 0x1000, MT_DEVICE | MT_RW | MT_NS) /* SEC SIM */
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/* For SCMI shared memory region */
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#define SRAM0_MAP MAP_REGION_FLAT(SRAM0_BASE, 0x1000, MT_RW | MT_DEVICE)
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#endif /* PLATFORM_DEF_H */
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