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7ae58c6ba7
PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree. Platform asserts the value read from the DT are the SoC addresses. Change-Id: I43f0890b51918a30c87ac067d3780ab27a0f59de Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/*
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* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2018-2019, Linaro Limited
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP_COMMON_H
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#define STM32MP_COMMON_H
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#include <stdbool.h>
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#include <arch_helpers.h>
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/* Functions to save and get boot context address given by ROM code */
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void stm32mp_save_boot_ctx_address(uintptr_t address);
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uintptr_t stm32mp_get_boot_ctx_address(void);
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/* Return the base address of the DDR controller */
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uintptr_t stm32mp_ddrctrl_base(void);
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/* Return the base address of the DDR PHY */
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uintptr_t stm32mp_ddrphyc_base(void);
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/* Return the base address of the PWR peripheral */
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uintptr_t stm32mp_pwr_base(void);
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/* Return the base address of the RCC peripheral */
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uintptr_t stm32mp_rcc_base(void);
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/*
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* Platform util functions for the GPIO driver
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* @bank: Target GPIO bank ID as per DT bindings
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*
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* Platform shall implement these functions to provide to stm32_gpio
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* driver the resource reference for a target GPIO bank. That are
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* memory mapped interface base address, interface offset (see below)
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* and clock identifier.
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*
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* stm32_get_gpio_bank_offset() returns a bank offset that is used to
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* check DT configuration matches platform implementation of the banks
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* description.
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*/
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uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
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unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
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uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
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/*
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* Util for clock gating and to get clock rate for stm32 and platform drivers
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* @id: Target clock ID, ID used in clock DT bindings
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*/
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bool stm32mp_clk_is_enabled(unsigned long id);
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int stm32mp_clk_enable(unsigned long id);
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int stm32mp_clk_disable(unsigned long id);
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unsigned long stm32mp_clk_get_rate(unsigned long id);
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/* Initialise the IO layer and register platform IO devices */
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void stm32mp_io_setup(void);
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static inline uint64_t arm_cnt_us2cnt(uint32_t us)
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{
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return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
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}
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static inline uint64_t timeout_init_us(uint32_t us)
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{
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return read_cntpct_el0() + arm_cnt_us2cnt(us);
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}
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static inline bool timeout_elapsed(uint64_t expire)
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{
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return read_cntpct_el0() > expire;
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}
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#endif /* STM32MP_COMMON_H */
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