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7ae58c6ba7
PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree. Platform asserts the value read from the DT are the SoC addresses. Change-Id: I43f0890b51918a30c87ac067d3780ab27a0f59de Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
42 lines
989 B
C
42 lines
989 B
C
/*
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* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <limits.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/st/stm32mp_reset.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#define RST_CLR_OFFSET 4U
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void stm32mp_reset_assert(uint32_t id)
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{
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uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t);
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uint32_t bit = id % (uint32_t)__LONG_BIT;
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uintptr_t rcc_base = stm32mp_rcc_base();
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mmio_write_32(rcc_base + offset, BIT(bit));
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while ((mmio_read_32(rcc_base + offset) & BIT(bit)) == 0U) {
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;
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}
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}
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void stm32mp_reset_deassert(uint32_t id)
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{
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uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) +
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RST_CLR_OFFSET;
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uint32_t bit = id % (uint32_t)__LONG_BIT;
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uintptr_t rcc_base = stm32mp_rcc_base();
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mmio_write_32(rcc_base + offset, BIT(bit));
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while ((mmio_read_32(rcc_base + offset) & BIT(bit)) != 0U) {
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;
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}
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}
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