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7ae58c6ba7
PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree. Platform asserts the value read from the DT are the SoC addresses. Change-Id: I43f0890b51918a30c87ac067d3780ab27a0f59de Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
20 lines
439 B
C
20 lines
439 B
C
/*
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* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <drivers/st/stm32mp1_ddr_helpers.h>
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#include <lib/mmio.h>
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void ddr_enable_clock(void)
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{
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mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR,
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RCC_DDRITFCR_DDRC1EN |
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RCC_DDRITFCR_DDRC2EN |
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RCC_DDRITFCR_DDRPHYCEN |
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RCC_DDRITFCR_DDRPHYCAPBEN |
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RCC_DDRITFCR_DDRCAPBEN);
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}
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