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https://github.com/ARM-software/arm-trusted-firmware.git
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7ac6a76c47
Add SPM suspend driver for suspend/resume features. TEST=build pass BUG=b:202871018 Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com> Change-Id: I25b4b97cd3138a7b347385539e47ccfa884d64fc
149 lines
3 KiB
C
149 lines
3 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <lib/psci/psci.h>
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#include <lib/spinlock.h>
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#include <mt_cpu_pm_cpc.h>
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#include <mt_lp_irqremain.h>
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#include <mt_lp_rm.h>
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#include <mt_mcdi.h>
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#include <plat_mtk_lpm.h>
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#include <plat_pm.h>
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DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1);
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static int plat_mt_lp_cpu_rc;
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static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state)
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{
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return 0;
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}
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static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state)
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{
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mtk_cpc_core_on_hint_clr(cpu);
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if (IS_SYSTEM_SUSPEND_STATE(state)) {
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mtk_cpc_time_sync();
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}
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return 0;
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}
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static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state)
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{
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return 0;
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}
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static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
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{
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/* clear DBGPRCR.CORENPDRQ to allow CPU power down */
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write_dbgprcr_el1(0ULL);
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return 0;
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}
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static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state)
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{
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return 0;
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}
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static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
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{
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return 0;
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}
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static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
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{
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if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
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return -1;
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}
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mtk_cpc_mcusys_off_reflect();
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return 0;
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}
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static int pwr_mcusys_pwron_finished(unsigned int cpu,
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const psci_power_state_t *state)
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{
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int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
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if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
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return -1;
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}
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mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
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mt_lp_irqremain_release();
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return 0;
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}
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static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
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{
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int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
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if (!IS_MCUSYS_OFF_STATE(state)) {
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goto mt_pwr_mcusysoff_break;
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}
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if (mcdi_try_init() != 0) { /* not ready to process mcusys-off */
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goto mt_pwr_mcusysoff_break;
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}
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if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
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goto mt_pwr_mcusysoff_break;
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}
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plat_mt_lp_cpu_rc =
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mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
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if (plat_mt_lp_cpu_rc < 0) {
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goto mt_pwr_mcusysoff_reflect;
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}
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mt_lp_irqremain_aquire();
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return 0;
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mt_pwr_mcusysoff_reflect:
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mtk_cpc_mcusys_off_reflect();
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mt_pwr_mcusysoff_break:
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plat_mt_lp_cpu_rc = -1;
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return -1;
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}
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static const struct mt_lpm_tz plat_pm = {
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.pwr_prompt = pwr_state_prompt,
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.pwr_reflect = pwr_state_reflect,
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.pwr_cpu_on = pwr_cpu_pwron,
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.pwr_cpu_dwn = pwr_cpu_pwrdwn,
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.pwr_cluster_on = pwr_cluster_pwron,
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.pwr_cluster_dwn = pwr_cluster_pwrdwn,
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.pwr_mcusys_dwn = pwr_mcusys_pwrdwn,
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.pwr_mcusys_on = pwr_mcusys_pwron,
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.pwr_mcusys_on_finished = pwr_mcusys_pwron_finished
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};
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const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
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{
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mtk_cpc_init();
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if (mcdi_try_init() == 0) {
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INFO("MCDI init done.\n");
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}
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mt_lp_irqremain_init();
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return &plat_pm;
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}
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