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7839a05090
The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver and DTS files are in include/dt-bindings/. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
94 lines
2 KiB
C
94 lines
2 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <boot_api.h>
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#include <console.h>
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#include <debug.h>
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#include <delay_timer.h>
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#include <desc_image_load.h>
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#include <generic_delay_timer.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <stm32mp1_clk.h>
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#include <stm32mp1_dt.h>
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#include <stm32mp1_private.h>
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#include <stm32mp1_pwr.h>
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#include <stm32mp1_rcc.h>
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#include <string.h>
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#include <xlat_tables_v2.h>
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void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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stm32mp1_save_boot_ctx_address(arg0);
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}
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void bl2_platform_setup(void)
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{
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INFO("BL2 runs SP_MIN setup\n");
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}
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void bl2_el3_plat_arch_setup(void)
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{
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/*
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* Disable the backup domain write protection.
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* The protection is enable at each reset by hardware
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* and must be disabled by software.
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*/
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mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP);
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while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) {
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;
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}
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/* Reset backup domain on cold boot cases */
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if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
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mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
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while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) ==
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0U) {
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;
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}
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mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
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}
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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/* Prevent corruption of preloaded BL32 */
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mmap_add_region(BL32_BASE, BL32_BASE,
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BL32_LIMIT - BL32_BASE,
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MT_MEMORY | MT_RO | MT_SECURE);
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/* Prevent corruption of preloaded Device Tree */
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mmap_add_region(DTB_BASE, DTB_BASE,
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DTB_LIMIT - DTB_BASE,
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MT_MEMORY | MT_RO | MT_SECURE);
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configure_mmu();
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generic_delay_timer_init();
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if (dt_open_and_check() < 0) {
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panic();
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}
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if (stm32mp1_clk_probe() < 0) {
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panic();
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}
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if (stm32mp1_clk_init() < 0) {
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panic();
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}
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stm32mp1_io_setup();
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}
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