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77feb745e4
Cortex-X3 erratum 3701769 that applies to r0p0, r1p0, r1p1 and r1p2 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2055130/latest/ Change-Id: Ifd722e1bb8616ada2ad158297a7ca80b19a3370b Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
/*
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Runtime C routines for errata workarounds and common routines */
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#include <arch.h>
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#include <arch_helpers.h>
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#include <cortex_a75.h>
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#include <cortex_a520.h>
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#include <cortex_a710.h>
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#include <cortex_a715.h>
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#include <cortex_a720.h>
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#include <cortex_a720_ae.h>
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#include <cortex_a725.h>
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#include <cortex_x2.h>
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#include <cortex_x3.h>
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#include <cortex_x4.h>
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#include <lib/cpus/cpu_ops.h>
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#include <lib/cpus/errata.h>
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#if ERRATA_A520_2938996 || ERRATA_X4_2726228
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unsigned int check_if_affected_core(void)
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{
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uint32_t midr_val = read_midr();
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long rev_var = cpu_get_rev_var();
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if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) {
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return check_erratum_cortex_a520_2938996(rev_var);
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} else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) {
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return check_erratum_cortex_x4_2726228(rev_var);
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}
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return ERRATA_NOT_APPLIES;
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}
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#endif
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#if ERRATA_A75_764081
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bool errata_a75_764081_applies(void)
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{
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long rev_var = cpu_get_rev_var();
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if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
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return true;
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}
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return false;
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}
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#endif /* ERRATA_A75_764081 */
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bool errata_ich_vmcr_el2_applies(void)
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{
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switch (EXTRACT_PARTNUM(read_midr())) {
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#if ERRATA_A710_3701772
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case EXTRACT_PARTNUM(CORTEX_A710_MIDR):
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if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A710_3701772 */
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#if ERRATA_A715_3699560
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case EXTRACT_PARTNUM(CORTEX_A715_MIDR):
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if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A715_3699560 */
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#if ERRATA_A720_3699561
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case EXTRACT_PARTNUM(CORTEX_A720_MIDR):
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if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;;
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break;
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#endif /* ERRATA_A720_3699561 */
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#if ERRATA_A720_AE_3699562
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case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR):
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if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A720_AE_3699562 */
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#if ERRATA_A725_3699564
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case EXTRACT_PARTNUM(CORTEX_A725_MIDR):
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if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A725_3699564 */
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#if ERRATA_X2_3701772
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case EXTRACT_PARTNUM(CORTEX_X2_MIDR):
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if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_X2_3701772 */
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#if ERRATA_X3_3701769
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case EXTRACT_PARTNUM(CORTEX_X3_MIDR):
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if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_X3_3701769 */
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default:
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break;
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}
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return false;
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}
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