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https://github.com/ARM-software/arm-trusted-firmware.git
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75530ee280
Add Centralized Power Control (CPC) module to manage CPU power states. Signed-off-by: Kai Liang <kai.liang@mediatek.com> Change-Id: I212155143018141c89427032f6a7d21243e750b7
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
/*
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* Copyright (c) 2025, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <plat/common/platform.h>
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#include <lib/pm/mtk_pm.h>
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#include <mcucfg.h>
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#include "mt_cpu_pm.h"
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#include "mt_ppu.h"
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#include "mt_smp.h"
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#define is_core_power_status_on(_pwr_ctrl)\
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(!!((mmio_read_32(_pwr_ctrl->pwr.ppu_pwsr)) & (PPU_PWSR_STATE_ON)))
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#ifndef CPU_PM_CORE_ARCH64_ONLY
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void mt_smp_core_init_arch(int cluster,
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int cpu,
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int arm64,
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struct cpu_pwr_ctrl *pwr_ctrl)
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{
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CPU_PM_ASSERT(cluster == 0);
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CPU_PM_ASSERT(pwr_ctrl);
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/* aa64naa32 in bits[16:23] */
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if (arm64)
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mmio_setbits_32(pwr_ctrl->arch_addr,
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BIT(AA64NAA32_FLAG_START_BIT + cpu));
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else
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mmio_clrbits_32(pwr_ctrl->arch_addr,
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BIT(AA64NAA32_FLAG_START_BIT + cpu));
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}
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#endif /* CPU_PM_CORE_ARCH64_ONLY */
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void mt_smp_core_bootup_address_set(int cluster,
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int cpu,
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struct cpu_pwr_ctrl *pwr_ctrl,
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uintptr_t entry)
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{
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CPU_PM_ASSERT(pwr_ctrl);
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/* Set bootup address */
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mmio_write_32(pwr_ctrl->rvbaraddr_l, entry);
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mmio_write_32(pwr_ctrl->rvbaraddr_h, 0);
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}
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int mt_smp_power_core_on(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl)
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{
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unsigned int val = 0;
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CPU_PM_ASSERT(pwr_ctrl);
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mt_smp_ppu_pwr_set(&pwr_ctrl->pwr, PPU_PWPR_DYNAMIC_MODE, PPU_PWPR_OFF);
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val = is_core_power_status_on(pwr_ctrl);
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if (!val) {
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mmio_clrbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
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GIC_WAKEUP_IGNORE(cpu_id));
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mmio_setbits_32(SPM_EXT_INT_WAKEUP_REQ_SET, BIT(cpu_id));
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mmio_clrbits_32(SPMC_CONTROL_CONFIG,
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SPMC_CPU_RESET_PWRON_CONFIG << (cpu_id));
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dsbsy();
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isb();
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while (!is_core_power_status_on(pwr_ctrl))
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DO_SMP_CORE_ON_WAIT_TIMEOUT(cpu_id, val);
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mmio_setbits_32(SPM_EXT_INT_WAKEUP_REQ_CLR, BIT(cpu_id));
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} else {
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mmio_clrbits_32(SPMC_CONTROL_CONFIG,
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SPMC_CPU_RESET_PWRON_CONFIG << (cpu_id));
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INFO("[%s:%d] - core_%u have been power on\n",
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__func__, __LINE__, cpu_id);
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}
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return MTK_CPUPM_E_OK;
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}
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int mt_smp_power_core_off(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl)
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{
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mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
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GIC_WAKEUP_IGNORE(cpu_id));
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return MTK_CPUPM_E_OK;
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}
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void mt_smp_init(void)
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{
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mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
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/* INFO=SPMC_INIT: clear resetpwron of mcusys/cluster/core0 */
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mmio_clrbits_32(SPMC_CONTROL_CONFIG, SPMC_MCUSYS_RESET_PWRON_CONFIG);
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mmio_clrbits_32(SPMC_CONTROL_CONFIG, SPMC_CPUTOP_RESET_PWRON_CONFIG);
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/* Switch DSU ISO/CKDIS control from PCSM to PPU */
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mmio_setbits_32(CPC_FCM_SPMC_SW_CFG2,
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(CPUSYS_PPU_CLK_EN_CTRL | CPUSYS_PPU_ISO_CTRL));
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#ifdef SPM_CPU_BUCK_ISO_CON
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/* Make sure that buck iso have been released before power on */
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mmio_write_32(SPM_CPU_BUCK_ISO_CON, SPM_CPU_BUCK_ISO_DEFAUT);
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#endif /* SPM_CPU_BUCK_ISO_CON */
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}
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