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https://github.com/ARM-software/arm-trusted-firmware.git
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75530ee280
Add Centralized Power Control (CPC) module to manage CPU power states. Signed-off-by: Kai Liang <kai.liang@mediatek.com> Change-Id: I212155143018141c89427032f6a7d21243e750b7
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/*
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* Copyright (c) 2025, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_PPU_H
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#define MT_PPU_H
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#include <lib/mmio.h>
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#include "mt_cpu_pm.h"
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/* PPU PWPR definition */
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#define PPU_PWPR_MASK 0xF
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#define PPU_PWPR_MODE_MASK 0x1
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#define PPU_PWPR_OFF 0
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#define PPU_PWPR_MEM_RET 2
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#define PPU_PWPR_FULL_RET 5
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#define PPU_PWPR_MEM_OFF 6
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#define PPU_PWPR_FUN_RET 7
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#define PPU_PWPR_ON 8
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#define PPU_PWPR_WARM_RESET 10
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#define PPU_PWPR_DYNAMIC_MODE BIT(8)
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#define PPU_PWPR_OP_MASK 0xF0000
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#define PPU_PWPR_OP_DYNAMIC_MODE BIT(24)
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#define PPU_PWPR_OP_MODE(_policy) (((_policy) << 16) & PPU_PWPR_OP_MASK)
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#define PPU_PWPR_OP_ONE_SLICE_SF_ONLY 0
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#define PPU_PWPR_OP_ONE_SLICE_HALF_DRAM 1
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#define PPU_PWPR_OP_ONE_SLICE_FULL_DRAM 3
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#define PPU_PWPR_OP_ALL_SLICE_SF_ONLY 4
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#define PPU_PWPR_OP_ALL_SLICE_HALF_DRAM 5
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#define PPU_PWPR_OP_ALL_SLICE_FULL_DRAM 7
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#define DSU_PPU_PWPR_OP_MODE_DEF (PPU_PWPR_OP_ONE_SLICE_HALF_DRAM)
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/* PPU PWSR definition */
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#define PPU_PWSR_STATE_ON BIT(3)
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#ifdef CPU_PM_ACP_FSM
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#define PPU_PWSR_OP_STATUS 0x30000
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#define PPU_OP_ST_SF_ONLY 0x0
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#endif /* CPU_PM_ACP_FSM */
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#define MT_PPU_DCDR0 0x00606060
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#define MT_PPU_DCDR1 0x00006060
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void mt_smp_ppu_pwr_set(struct ppu_pwr_ctrl *ctrl,
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unsigned int mode,
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unsigned int policy);
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void mt_smp_ppu_op_set(struct ppu_pwr_ctrl *ctrl,
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unsigned int mode,
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unsigned int policy);
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void mt_smp_ppu_pwr_dynamic_set(struct ppu_pwr_ctrl *ctrl,
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unsigned int policy);
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void mt_smp_ppu_pwr_static_set(struct ppu_pwr_ctrl *ctrl,
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unsigned int policy);
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void mt_smp_ppu_set(struct ppu_pwr_ctrl *ctrl,
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unsigned int op_mode,
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unsigned int policy,
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unsigned int pwr_mode,
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unsigned int pwr_policy);
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#endif /* MT_PPU_H */
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