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7455cd1721
When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0) and then subsequently read in Non-secure state (SCR_EL3.NS==1), a wrong value might be returned. The same issue exists in the opposite way. Adding workaround in EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. For example, EL3 software should set SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for Non-secure(or Realm) state. EL3 software should clear SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for Secure state. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest/ Change-Id: I9f0403601c6346276e925f02eab55908b009d957 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ERRATA_H
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#define ERRATA_H
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#include <lib/cpus/cpu_ops.h>
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#define ERRATUM_WA_FUNC_SIZE CPU_WORD_SIZE
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#define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE
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#define ERRATUM_ID_SIZE 4
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#define ERRATUM_CVE_SIZE 2
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#define ERRATUM_CHOSEN_SIZE 1
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#define ERRATUM_MITIGATED_SIZE 1
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#define ERRATUM_WA_FUNC 0
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#define ERRATUM_CHECK_FUNC ERRATUM_WA_FUNC + ERRATUM_WA_FUNC_SIZE
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#define ERRATUM_ID ERRATUM_CHECK_FUNC + ERRATUM_CHECK_FUNC_SIZE
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#define ERRATUM_CVE ERRATUM_ID + ERRATUM_ID_SIZE
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#define ERRATUM_CHOSEN ERRATUM_CVE + ERRATUM_CVE_SIZE
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#define ERRATUM_MITIGATED ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE
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#define ERRATUM_ENTRY_SIZE ERRATUM_MITIGATED + ERRATUM_MITIGATED_SIZE
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/* Errata status */
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#define ERRATA_NOT_APPLIES 0
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#define ERRATA_APPLIES 1
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#define ERRATA_MISSING 2
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#ifndef __ASSEMBLER__
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#include <lib/cassert.h>
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void print_errata_status(void);
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/*
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* NOTE that this structure will be different on AArch32 and AArch64. The
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* uintptr_t will reflect the change and the alignment will be correct in both.
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*/
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struct erratum_entry {
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uintptr_t (*wa_func)(uint64_t cpu_rev);
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uintptr_t (*check_func)(uint64_t cpu_rev);
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/* Will fit CVEs with up to 10 character in the ID field */
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uint32_t id;
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/* Denote CVEs with their year or errata with 0 */
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uint16_t cve;
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uint8_t chosen;
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/* TODO(errata ABI): placeholder for the mitigated field */
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uint8_t _mitigated;
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} __packed;
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CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE,
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assert_erratum_entry_asm_c_different_sizes);
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/*
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* Runtime errata helpers.
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*/
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#if ERRATA_A75_764081
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bool errata_a75_764081_applies(void);
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#else
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static inline bool errata_a75_764081_applies(void)
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{
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return false;
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}
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#endif
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#if ERRATA_A520_2938996 || ERRATA_X4_2726228
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unsigned int check_if_affected_core(void);
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#endif
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int check_wa_cve_2024_7881(void);
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bool errata_ich_vmcr_el2_applies(void);
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#else
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/*
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* errata framework macro helpers
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*
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* NOTE an erratum and CVE id could clash. However, both numbers are very large
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* and the probablity is minuscule. Working around this makes code very
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* complicated and extremely difficult to read so it is not considered. In the
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* unlikely event that this does happen, prepending the CVE id with a 0 should
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* resolve the conflict
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*/
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#define ERRATUM(id) 0, id
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#define CVE(year, id) year, id
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#define NO_ISB 1
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#define NO_ASSERT 0
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#define NO_APPLY_AT_RESET 0
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#define APPLY_AT_RESET 1
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#define GET_CPU_REV 1
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#define NO_GET_CPU_REV 0
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/* useful for errata that end up always being worked around */
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#define ERRATUM_ALWAYS_CHOSEN 1
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#endif /* __ASSEMBLER__ */
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/* Macro to get CPU revision code for checking errata version compatibility. */
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#define CPU_REV(r, p) ((r << 4) | p)
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#endif /* ERRATA_H */
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