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742ca2307f
This change makes AMU auxiliary counters configurable on a per-core
basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`.
Auxiliary counters can be described via the `HW_CONFIG` device tree if
the `ENABLE_AMU_FCONF` build option is enabled, or the platform must
otherwise implement the `plat_amu_topology` function.
A new phandle property for `cpu` nodes (`amu`) has been introduced to
the `HW_CONFIG` specification to allow CPUs to describe the view of
their own AMU:
```
cpu0: cpu@0 {
...
amu = <&cpu0_amu>;
};
```
Multiple cores may share an `amu` handle if they implement the
same set of auxiliary counters.
AMU counters are described for one or more AMUs through the use of a new
`amus` node:
```
amus {
cpu0_amu: amu-0 {
#address-cells = <1>;
#size-cells = <0>;
counter@0 {
reg = <0>;
enable-at-el3;
};
counter@n {
reg = <n>;
...
};
};
};
```
This structure describes the **auxiliary** (group 1) AMU counters.
Architected counters have architecturally-defined behaviour, and as
such do not require DTB entries.
These `counter` nodes support two properties:
- The `reg` property represents the counter register index.
- The presence of the `enable-at-el3` property determines whether
the firmware should enable the counter prior to exiting EL3.
Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|---|---|---|
| .. | ||
| fconf | ||
| measured_boot | ||
| spd | ||
| activity-monitors.rst | ||
| arm-sip-service.rst | ||
| cot-binding.rst | ||
| debugfs-design.rst | ||
| exception-handling.rst | ||
| ffa-manifest-binding.rst | ||
| firmware-update.rst | ||
| index.rst | ||
| platform-interrupt-controller-API.rst | ||
| ras.rst | ||
| realm-management-extension.rst | ||
| romlib-design.rst | ||
| sdei.rst | ||
| secure-partition-manager-mm.rst | ||
| secure-partition-manager.rst | ||
| xlat-tables-lib-v2-design.rst | ||