mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
741dd04c81
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0, and r1p1 of the V1 processor core, and it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52
32 lines
1.3 KiB
C
32 lines
1.3 KiB
C
/*
|
|
* Copyright (c) 2019-2021, ARM Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef NEOVERSE_V1_H
|
|
#define NEOVERSE_V1_H
|
|
|
|
#define NEOVERSE_V1_MIDR U(0x410FD400)
|
|
|
|
/*******************************************************************************
|
|
* CPU Extended Control register specific definitions.
|
|
******************************************************************************/
|
|
#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
|
|
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
|
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
|
|
|
|
/*******************************************************************************
|
|
* CPU Power Control register specific definitions
|
|
******************************************************************************/
|
|
#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
|
#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register specific definitions.
|
|
******************************************************************************/
|
|
#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
|
|
#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
|
#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
|
|
|
|
#endif /* NEOVERSE_V1_H */
|