Jayanth Dodderi Chidanand a0d9a973a4 chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code ... SCTLR_EL1 and TCR_EL1 regs are included either as part of errata "ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure. The code to write and read into these context entries, looks repetitive and is invoked at most places. This section is refactored to bring them under a static procedure, keeping the code neat and easier to maintain. Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>		2024-08-21 08:45:25 +01:00
..
arm_arch_svc	chore: simplify the macro names in ENABLE_FEAT mechanism	2024-05-02 08:53:01 -05:00
el3	refactor(smccc): move pmf to vendor el3 calls	2024-05-06 09:42:11 -05:00
oem/chromeos	feat(cros_widevine): add ChromeOS widevine SMC handler	2024-02-02 16:41:21 +08:00
spd	feat(trusty): switch to simd_ctx_save/restore apis	2024-08-19 11:11:14 -05:00
std_svc	chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code	2024-08-21 08:45:25 +01:00