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73680c230f
Introduce driver for STM32 IWDG peripheral (Independent Watchdog). It is configured according to device tree content and should be enabled from there. The watchdog is not started by default. It can be started after an HW reset if the dedicated OTP is fused. The watchdog also needs to be frozen if a debugger is attached. This is done by configuring the correct bits in DBGMCU. This configuration is allowed by checking BSEC properties. An increase of BL2 size is also required when adding this new code. Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
144 lines
2.7 KiB
C
144 lines
2.7 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <drivers/st/stm32_iwdg.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
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STM32MP_SYSRAM_SIZE, \
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MT_MEMORY | \
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MT_RW | \
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MT_SECURE | \
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MT_EXECUTE_NEVER)
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#define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
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STM32MP1_DEVICE1_SIZE, \
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MT_DEVICE | \
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MT_RW | \
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MT_SECURE | \
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MT_EXECUTE_NEVER)
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#define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
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STM32MP1_DEVICE2_SIZE, \
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MT_DEVICE | \
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MT_RW | \
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MT_SECURE | \
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MT_EXECUTE_NEVER)
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#if defined(IMAGE_BL2)
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static const mmap_region_t stm32mp1_mmap[] = {
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MAP_SRAM,
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MAP_DEVICE1,
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MAP_DEVICE2,
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{0}
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};
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#endif
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#if defined(IMAGE_BL32)
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static const mmap_region_t stm32mp1_mmap[] = {
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MAP_SRAM,
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MAP_DEVICE1,
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MAP_DEVICE2,
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{0}
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};
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#endif
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void configure_mmu(void)
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{
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mmap_add(stm32mp1_mmap);
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init_xlat_tables();
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enable_mmu_svc_mon(0);
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}
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unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return GPIOZ;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return GPIOA + (bank - GPIO_BANK_A);
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}
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uint32_t stm32_iwdg_get_instance(uintptr_t base)
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{
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switch (base) {
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case IWDG1_BASE:
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return IWDG1_INST;
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case IWDG2_BASE:
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return IWDG2_INST;
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default:
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panic();
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}
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}
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uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
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{
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uint32_t iwdg_cfg = 0U;
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uint32_t otp_value;
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#if defined(IMAGE_BL2)
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if (bsec_shadow_register(HW2_OTP) != BSEC_OK) {
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panic();
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}
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#endif
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if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) {
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panic();
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}
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if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) {
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iwdg_cfg |= IWDG_HW_ENABLED;
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}
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if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) {
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iwdg_cfg |= IWDG_DISABLE_ON_STOP;
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}
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if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) {
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iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
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}
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return iwdg_cfg;
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}
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#if defined(IMAGE_BL2)
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uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
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{
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uint32_t otp;
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uint32_t result;
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if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) {
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panic();
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}
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if ((flags & IWDG_DISABLE_ON_STOP) != 0U) {
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otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS);
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}
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if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) {
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otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS);
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}
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result = bsec_write_otp(otp, HW2_OTP);
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if (result != BSEC_OK) {
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return result;
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}
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/* Sticky lock OTP_IWDG (read and write) */
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if (!bsec_write_sr_lock(HW2_OTP, 1U) ||
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!bsec_write_sw_lock(HW2_OTP, 1U)) {
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return BSEC_LOCK_FAIL;
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}
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return BSEC_OK;
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}
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#endif
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