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727bbf680d
As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <libfdt.h>
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#include "fpga_private.h"
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#include <plat/common/platform.h>
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#include <platform_def.h>
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static entry_point_info_t bl33_image_ep_info;
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volatile uint32_t secondary_core_spinlock;
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return 0ULL;
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#endif
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}
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uint32_t fpga_get_spsr_for_bl33_entry(void)
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{
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return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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/* Add this core to the VALID mpids list */
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fpga_valid_mpids[plat_my_core_pos()] = VALID_MPID;
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/*
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* Notify the secondary CPUs that the C runtime is ready
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* so they can announce themselves.
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*/
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secondary_core_spinlock = C_RUNTIME_READY_KEY;
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dsbish();
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sev();
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fpga_console_init();
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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/* Set x0-x3 for the primary CPU as expected by the kernel */
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bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE;
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bl33_image_ep_info.args.arg1 = 0U;
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bl33_image_ep_info.args.arg2 = 0U;
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bl33_image_ep_info.args.arg3 = 0U;
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}
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void bl31_plat_arch_setup(void)
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{
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}
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void bl31_platform_setup(void)
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{
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/* Write frequency to CNTCRL and initialize timer */
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generic_delay_timer_init();
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/*
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* Before doing anything else, wait for some time to ensure that
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* the secondary CPUs have populated the fpga_valid_mpids array.
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* As the number of secondary cores is unknown and can even be 0,
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* it is not possible to rely on any signal from them, so use a
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* delay instead.
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*/
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mdelay(5);
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/*
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* On the event of a cold reset issued by, for instance, a reset pin
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* assertion, we cannot guarantee memory to be initialized to zero.
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* In such scenario, if the secondary cores reached
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* plat_secondary_cold_boot_setup before the primary one initialized
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* .BSS, we could end up having a race condition if the spinlock
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* was not cleared before.
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*
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* Similarly, if there were a reset before the spinlock had been
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* cleared, the secondary cores would find the lock opened before
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* .BSS is cleared, causing another race condition.
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*
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* So clean the spinlock as soon as we think it is safe to reduce the
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* chances of any race condition on a reset.
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*/
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secondary_core_spinlock = 0UL;
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/* Initialize the GIC driver, cpu and distributor interfaces */
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plat_fpga_gic_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = &bl33_image_ep_info;
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/* Only expecting BL33: the kernel will run in EL2NS */
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assert(type == NON_SECURE);
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/* None of the images can have 0x0 as the entrypoint */
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if (next_image_info->pc) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
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int node;
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node = fdt_node_offset_by_compatible(fdt, 0, "arm,armv8-timer");
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if (node < 0) {
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return FPGA_DEFAULT_TIMER_FREQUENCY;
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}
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return fdt_read_uint32_default(fdt, node, "clock-frequency",
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FPGA_DEFAULT_TIMER_FREQUENCY);
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}
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void bl31_plat_enable_mmu(uint32_t flags)
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{
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/* TODO: determine if MMU needs to be enabled */
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}
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