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https://github.com/ARM-software/arm-trusted-firmware.git
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dfa6c54071
The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:
Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."
Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."
The following files in fdts\
fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts
describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
, see include\dt-bindings\interrupt-controller\arm-gic.h:
which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware
This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.
Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
221 lines
5 KiB
Text
221 lines
5 KiB
Text
/*
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/memreserve/ 0x80000000 0x00010000;
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/ {
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};
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/ {
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model = "FVP Base";
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compatible = "arm,vfp-base", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0x84000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU_MAP
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <150>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <500>;
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exit-latency-us = <1000>;
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min-residency-us = <2500>;
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};
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};
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CPUS
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x7F000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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};
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gic: interrupt-controller@2f000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x2f000000 0 0x10000>, // GICD
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<0x0 0x2f100000 0 0x200000>, // GICR
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<0x0 0x2c000000 0 0x2000>, // GICC
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<0x0 0x2c010000 0 0x2000>, // GICH
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<0x0 0x2c02f000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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its: its@2f020000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <100000000>;
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};
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timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <100000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <0 26 4>;
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reg = <0x0 0x2a830000 0x0 0x10000>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 60 4>,
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<0 61 4>,
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<0 62 4>,
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<0 63 4>;
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
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<0 0 1 &gic 0 0 0 1 4>,
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<0 0 2 &gic 0 0 0 2 4>,
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<0 0 3 &gic 0 0 0 3 4>,
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<0 0 4 &gic 0 0 0 4 4>,
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<0 0 5 &gic 0 0 0 5 4>,
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<0 0 6 &gic 0 0 0 6 4>,
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<0 0 7 &gic 0 0 0 7 4>,
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<0 0 8 &gic 0 0 0 8 4>,
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<0 0 9 &gic 0 0 0 9 4>,
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<0 0 10 &gic 0 0 0 10 4>,
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<0 0 11 &gic 0 0 0 11 4>,
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<0 0 12 &gic 0 0 0 12 4>,
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<0 0 13 &gic 0 0 0 13 4>,
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<0 0 14 &gic 0 0 0 14 4>,
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<0 0 15 &gic 0 0 0 15 4>,
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<0 0 16 &gic 0 0 0 16 4>,
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<0 0 17 &gic 0 0 0 17 4>,
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<0 0 18 &gic 0 0 0 18 4>,
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<0 0 19 &gic 0 0 0 19 4>,
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<0 0 20 &gic 0 0 0 20 4>,
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<0 0 21 &gic 0 0 0 21 4>,
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<0 0 22 &gic 0 0 0 22 4>,
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<0 0 23 &gic 0 0 0 23 4>,
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<0 0 24 &gic 0 0 0 24 4>,
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<0 0 25 &gic 0 0 0 25 4>,
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<0 0 26 &gic 0 0 0 26 4>,
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<0 0 27 &gic 0 0 0 27 4>,
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<0 0 28 &gic 0 0 0 28 4>,
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<0 0 29 &gic 0 0 0 29 4>,
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<0 0 30 &gic 0 0 0 30 4>,
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<0 0 31 &gic 0 0 0 31 4>,
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<0 0 32 &gic 0 0 0 32 4>,
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<0 0 33 &gic 0 0 0 33 4>,
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<0 0 34 &gic 0 0 0 34 4>,
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<0 0 35 &gic 0 0 0 35 4>,
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<0 0 36 &gic 0 0 0 36 4>,
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<0 0 37 &gic 0 0 0 37 4>,
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<0 0 38 &gic 0 0 0 38 4>,
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<0 0 39 &gic 0 0 0 39 4>,
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<0 0 40 &gic 0 0 0 40 4>,
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<0 0 41 &gic 0 0 0 41 4>,
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<0 0 42 &gic 0 0 0 42 4>;
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#include "rtsm_ve-motherboard-aarch32.dtsi"
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};
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panels {
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panel@0 {
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compatible = "panel";
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mode = "XVGA";
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refresh = <60>;
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xres = <1024>;
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yres = <768>;
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pixclock = <15748>;
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left_margin = <152>;
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right_margin = <48>;
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upper_margin = <23>;
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lower_margin = <3>;
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hsync_len = <104>;
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vsync_len = <4>;
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sync = <0>;
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vmode = "FB_VMODE_NONINTERLACED";
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tim2 = "TIM2_BCD", "TIM2_IPC";
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cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
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caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
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bpp = <16>;
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};
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};
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};
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