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https://github.com/ARM-software/arm-trusted-firmware.git
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71c40d3bb7
Add a simple CSU driver for i.MX8M family. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I0eda3561e7a38a232acdb8e043c7200c630f7e22
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* Copyright 2020-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <imx8m_csu.h>
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void imx_csu_init(const struct imx_csu_cfg *csu_cfg)
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{
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const struct imx_csu_cfg *csu = csu_cfg;
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uint32_t val;
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while (csu->type != CSU_INVALID) {
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switch (csu->type) {
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case CSU_CSL:
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val = mmio_read_32(CSLx_REG(csu->idx));
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if (val & CSLx_LOCK(csu->idx)) {
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break;
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}
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mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx),
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CSLx_CFG(csu->csl_level | (csu->lock << 8), csu->idx));
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break;
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case CSU_HP:
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val = mmio_read_32(CSU_HP_REG(csu->idx));
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if (val & CSU_HP_LOCK(csu->idx)) {
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break;
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}
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mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx),
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CSU_HP_CFG(csu->hp | (csu->lock << 0x1), csu->idx));
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break;
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case CSU_SA:
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val = mmio_read_32(CSU_SA_REG(csu->idx));
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if (val & CSU_SA_LOCK(csu->idx)) {
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break;
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}
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mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx),
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CSU_SA_CFG(csu->sa | (csu->lock << 0x1), csu->idx));
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break;
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case CSU_HPCONTROL:
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val = mmio_read_32(CSU_HPCONTROL_REG(csu->idx));
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if (val & CSU_HPCONTROL_LOCK(csu->idx)) {
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break;
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}
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mmio_clrsetbits_32(CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx),
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CSU_HPCONTROL_CFG(csu->hpctrl | (csu->lock << 0x1), csu->idx));
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break;
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default:
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break;
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}
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csu++;
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}
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}
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