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ece8f7d734
These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect
EL2 (and lower) execution. Each feat_init_el3() is called long before
any lower EL has had a chance to execute, so setting the bits at reset
is redundant. Removing them from reset code also improves readability of
the immutable EL3 state.
Preserve the original intention for the TTA bit of "enabled for NS and
disabled everywhere else" (inferred from commit messages d4582d3088 and
2031d6166a and the comment). This is because CPTR_EL3 will be contexted
and so everyone will eventually get whatever NS has anyway.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3d24b45d3ea80882c8e450b2d9db9d5531facec1
42 lines
855 B
C
42 lines
855 B
C
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SYS_REG_TRACE_H
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#define SYS_REG_TRACE_H
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#include <context.h>
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#if ENABLE_SYS_REG_TRACE_FOR_NS
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#if __aarch64__
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void sys_reg_trace_enable(cpu_context_t *context);
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void sys_reg_trace_disable(cpu_context_t *context);
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void sys_reg_trace_init_el2_unused(void);
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#else
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void sys_reg_trace_init_el3(void);
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#endif /* __aarch64__ */
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#else /* !ENABLE_SYS_REG_TRACE_FOR_NS */
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#if __aarch64__
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static inline void sys_reg_trace_enable(cpu_context_t *context)
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{
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}
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static inline void sys_reg_trace_disable(cpu_context_t *context)
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{
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}
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static inline void sys_reg_trace_init_el2_unused(void)
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{
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}
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#else
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static inline void sys_reg_trace_init_el3(void)
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{
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}
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#endif /* __aarch64__ */
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#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
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#endif /* SYS_REG_TRACE_H */
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