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https://github.com/ARM-software/arm-trusted-firmware.git
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c97857dba2
New SoC is a78 based with gicv3 and uart over pl011. Communication interfaces are similar to Versal NET platform. System starts with AMD PLM firmware which loads TF-A(bl31) to memory, which is already configured, and jumps to it. PLM also prepare handoff structure for TF-A with information what components were load and flags which indicate which EL level SW should be started. Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c Signed-off-by: Amit Nagal <amit.nagal@amd.com> Signed-off-by: Akshay Belsare <akshay.belsare@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/*
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* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Versal Gen 2 IPI management enums and defines */
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#ifndef PLAT_IPI_H
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#define PLAT_IPI_H
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#include <stdint.h>
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#include <ipi.h>
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/*********************************************************************
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* IPI agent IDs macros
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********************************************************************/
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#define IPI_ID_PMC 1U
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#define IPI_ID_APU 2U
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#define IPI_ID_RPU0 3U
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#define IPI_ID_RPU1 4U
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#define IPI_ID_3 5U
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#define IPI_ID_4 6U
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#define IPI_ID_5 7U
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#define IPI_ID_MAX 8U
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/*********************************************************************
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* IPI message buffers
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********************************************************************/
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#define IPI_BUFFER_BASEADDR (0xEB3F0000U)
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#define IPI_LOCAL_ID IPI_ID_APU
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#define IPI_REMOTE_ID IPI_ID_PMC
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#define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U))
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#define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U))
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#define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U)
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#define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U)
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#define IPI_BUFFER_MAX_WORDS 8
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#define IPI_BUFFER_REQ_OFFSET 0x0U
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#define IPI_BUFFER_RESP_OFFSET 0x20U
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/*********************************************************************
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* Platform specific IPI API declarations
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********************************************************************/
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/* Configure IPI table */
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extern void soc_ipi_config_table_init(void);
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/*******************************************************************************
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* IPI registers and bitfields
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******************************************************************************/
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#define IPI0_REG_BASE (0xEB330000U)
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#define IPI0_TRIG_BIT (1 << 2)
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#define PMC_IPI_TRIG_BIT (1 << 1)
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#define IPI1_REG_BASE (0xEB340000U)
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#define IPI1_TRIG_BIT (1 << 3)
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#define IPI2_REG_BASE (0xEB350000U)
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#define IPI2_TRIG_BIT (1 << 4)
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#define IPI3_REG_BASE (0xEB360000U)
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#define IPI3_TRIG_BIT (1 << 5)
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#define IPI4_REG_BASE (0xEB370000U)
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#define IPI4_TRIG_BIT (1 << 6)
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#define IPI5_REG_BASE (0xEB380000U)
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#define IPI5_TRIG_BIT (1 << 7)
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#endif /* PLAT_IPI_H */
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