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https://github.com/ARM-software/arm-trusted-firmware.git
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6e19bd563d
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
265 lines
8.5 KiB
C
265 lines
8.5 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gic_common.h>
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#include "../common/gic_common_private.h"
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#include "gicv3_private.h"
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/******************************************************************************
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* This function marks the core as awake in the re-distributor and
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* ensures that the interface is active.
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*****************************************************************************/
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void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
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{
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/*
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* The WAKER_PS_BIT should be changed to 0
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* only when WAKER_CA_BIT is 1.
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*/
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assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
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/* Mark the connected core as awake */
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gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
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/* Wait till the WAKER_CA_BIT changes to 0 */
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while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U)
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;
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}
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/******************************************************************************
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* This function marks the core as asleep in the re-distributor and ensures
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* that the interface is quiescent.
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*****************************************************************************/
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void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
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{
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/* Mark the connected core as asleep */
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gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
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/* Wait till the WAKER_CA_BIT changes to 1 */
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while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U)
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;
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}
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/*******************************************************************************
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* This function probes the Redistributor frames when the driver is initialised
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* and saves their base addresses. These base addresses are used later to
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* initialise each Redistributor interface.
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******************************************************************************/
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void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
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unsigned int rdistif_num,
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uintptr_t gicr_base,
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mpidr_hash_fn mpidr_to_core_pos)
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{
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u_register_t mpidr;
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unsigned int proc_num;
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uint64_t typer_val;
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uintptr_t rdistif_base = gicr_base;
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assert(rdistif_base_addrs != NULL);
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/*
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* Iterate over the Redistributor frames. Store the base address of each
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* frame in the platform provided array. Use the "Processor Number"
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* field to index into the array if the platform has not provided a hash
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* function to convert an MPIDR (obtained from the "Affinity Value"
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* field into a linear index.
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*/
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do {
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typer_val = gicr_read_typer(rdistif_base);
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if (mpidr_to_core_pos != NULL) {
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mpidr = mpidr_from_gicr_typer(typer_val);
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proc_num = mpidr_to_core_pos(mpidr);
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} else {
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proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
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TYPER_PROC_NUM_MASK;
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}
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if (proc_num < rdistif_num)
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rdistif_base_addrs[proc_num] = rdistif_base;
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rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
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} while ((typer_val & TYPER_LAST_BIT) == 0U);
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}
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/*******************************************************************************
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* Helper function to configure the default attributes of SPIs.
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******************************************************************************/
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void gicv3_spis_config_defaults(uintptr_t gicd_base)
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{
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unsigned int index, num_ints;
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num_ints = gicd_read_typer(gicd_base);
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num_ints &= TYPER_IT_LINES_NO_MASK;
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num_ints = (num_ints + 1U) << 5;
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/*
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* Treat all SPIs as G1NS by default. The number of interrupts is
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* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
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*/
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for (index = MIN_SPI_ID; index < num_ints; index += 32U)
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gicd_write_igroupr(gicd_base, index, ~0U);
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/* Setup the default SPI priorities doing four at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 4U)
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gicd_write_ipriorityr(gicd_base,
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index,
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GICD_IPRIORITYR_DEF_VAL);
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/*
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* Treat all SPIs as level triggered by default, write 16 at
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* a time
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*/
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for (index = MIN_SPI_ID; index < num_ints; index += 16U)
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gicd_write_icfgr(gicd_base, index, 0U);
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}
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/*******************************************************************************
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* Helper function to configure properties of secure SPIs
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******************************************************************************/
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unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
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const interrupt_prop_t *interrupt_props,
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unsigned int interrupt_props_num)
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{
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unsigned int i;
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const interrupt_prop_t *current_prop;
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unsigned long long gic_affinity_val;
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unsigned int ctlr_enable = 0U;
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/* Make sure there's a valid property array */
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if (interrupt_props_num > 0U)
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assert(interrupt_props != NULL);
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for (i = 0U; i < interrupt_props_num; i++) {
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current_prop = &interrupt_props[i];
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if (current_prop->intr_num < MIN_SPI_ID)
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continue;
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/* Configure this interrupt as a secure interrupt */
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gicd_clr_igroupr(gicd_base, current_prop->intr_num);
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/* Configure this interrupt as G0 or a G1S interrupt */
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assert((current_prop->intr_grp == INTR_GROUP0) ||
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(current_prop->intr_grp == INTR_GROUP1S));
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if (current_prop->intr_grp == INTR_GROUP1S) {
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gicd_set_igrpmodr(gicd_base, current_prop->intr_num);
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ctlr_enable |= CTLR_ENABLE_G1S_BIT;
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} else {
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gicd_clr_igrpmodr(gicd_base, current_prop->intr_num);
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ctlr_enable |= CTLR_ENABLE_G0_BIT;
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}
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/* Set interrupt configuration */
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gicd_set_icfgr(gicd_base, current_prop->intr_num,
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current_prop->intr_cfg);
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/* Set the priority of this interrupt */
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gicd_set_ipriorityr(gicd_base, current_prop->intr_num,
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current_prop->intr_pri);
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/* Target SPIs to the primary CPU */
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gic_affinity_val =
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gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
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gicd_write_irouter(gicd_base, current_prop->intr_num,
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gic_affinity_val);
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/* Enable this interrupt */
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gicd_set_isenabler(gicd_base, current_prop->intr_num);
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}
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return ctlr_enable;
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}
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/*******************************************************************************
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* Helper function to configure the default attributes of SPIs.
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******************************************************************************/
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void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
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{
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unsigned int index;
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/*
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* Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
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* more scalable approach as it avoids clearing the enable bits in the
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* GICD_CTLR
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*/
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gicr_write_icenabler0(gicr_base, ~0U);
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gicr_wait_for_pending_write(gicr_base);
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/* Treat all SGIs/PPIs as G1NS by default. */
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gicr_write_igroupr0(gicr_base, ~0U);
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/* Setup the default PPI/SGI priorities doing four at a time */
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for (index = 0U; index < MIN_SPI_ID; index += 4U)
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gicr_write_ipriorityr(gicr_base,
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index,
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GICD_IPRIORITYR_DEF_VAL);
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/* Configure all PPIs as level triggered by default */
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gicr_write_icfgr1(gicr_base, 0U);
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}
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/*******************************************************************************
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* Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
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******************************************************************************/
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unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
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const interrupt_prop_t *interrupt_props,
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unsigned int interrupt_props_num)
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{
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unsigned int i;
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const interrupt_prop_t *current_prop;
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unsigned int ctlr_enable = 0U;
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/* Make sure there's a valid property array */
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if (interrupt_props_num > 0U)
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assert(interrupt_props != NULL);
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for (i = 0U; i < interrupt_props_num; i++) {
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current_prop = &interrupt_props[i];
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if (current_prop->intr_num >= MIN_SPI_ID)
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continue;
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/* Configure this interrupt as a secure interrupt */
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gicr_clr_igroupr0(gicr_base, current_prop->intr_num);
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/* Configure this interrupt as G0 or a G1S interrupt */
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assert((current_prop->intr_grp == INTR_GROUP0) ||
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(current_prop->intr_grp == INTR_GROUP1S));
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if (current_prop->intr_grp == INTR_GROUP1S) {
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gicr_set_igrpmodr0(gicr_base, current_prop->intr_num);
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ctlr_enable |= CTLR_ENABLE_G1S_BIT;
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} else {
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gicr_clr_igrpmodr0(gicr_base, current_prop->intr_num);
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ctlr_enable |= CTLR_ENABLE_G0_BIT;
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}
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/* Set the priority of this interrupt */
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gicr_set_ipriorityr(gicr_base, current_prop->intr_num,
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current_prop->intr_pri);
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/*
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* Set interrupt configuration for PPIs. Configuration for SGIs
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* are ignored.
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*/
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if ((current_prop->intr_num >= MIN_PPI_ID) &&
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(current_prop->intr_num < MIN_SPI_ID)) {
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gicr_set_icfgr1(gicr_base, current_prop->intr_num,
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current_prop->intr_cfg);
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}
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/* Enable this interrupt */
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gicr_set_isenabler0(gicr_base, current_prop->intr_num);
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}
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return ctlr_enable;
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}
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