Madhukar Pappireddy 6d5319afec feat(simd): add routines to save, restore sve state ... This adds assembly routines to save and restore SVE registers. In order to share between FPU and SVE the code to save and restore FPCR and FPSR, the patch converts code for those registers into macro. Since we will be using simd_ctx_t to save and restore FPU also, we use offsets in simd_ctx_t for FPSR and FPCR. Since simd_ctx_t has the same structure at the beginning as fp_regs_t, those offsets should be the same as CTX_FP_* offsets, when SVE is not enabled. Note that the code also saves and restores FPEXC32 reg along with FPSR and FPCR. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: I120c02359794aa6bb6376a464a9afe98bd84ae60		2024-08-19 11:10:10 -05:00
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aarch32	refactor(cpufeat): add macro to simplify is_feat_xx_present	2024-05-02 12:16:16 -05:00
aarch64	feat(simd): add routines to save, restore sve state	2024-08-19 11:10:10 -05:00
cpu_data_array.c	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00