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https://github.com/ARM-software/arm-trusted-firmware.git
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55df84f974
In Armada 8K DB boards, PCIe initialization can be executed only once because PCIe reset performed during chip power on and it cannot be executed via GPIO later. This means that power on can be executed only once, when it's called from the bootloader. Power on: Read bit 21 of the mode, it marks if the caller is the bootloader or the Linux Kernel. Power off: Check if the comphy was already configured to PCIe, if yes, check if the caller is bootloader, if both conditions are true (PCIe mode and called by Linux) - skip the power-off. In addition, fix incorrect documentation describing mode fields - PCIe width is 3 bits, not 2. NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work with it). Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
138 lines
3.5 KiB
C
138 lines
3.5 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <ap_setup.h>
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#include <cache_llc.h>
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#include <debug.h>
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#include <marvell_plat_priv.h>
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#include <plat_marvell.h>
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#include <runtime_svc.h>
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#include <smccc.h>
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#include "comphy/phy-comphy-cp110.h"
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/* #define DEBUG_COMPHY */
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#ifdef DEBUG_COMPHY
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#define debug(format...) NOTICE(format)
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#else
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#define debug(format, arg...)
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#endif
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/* Comphy related FID's */
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#define MV_SIP_COMPHY_POWER_ON 0x82000001
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#define MV_SIP_COMPHY_POWER_OFF 0x82000002
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#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
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#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
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#define MV_SIP_COMPHY_DIG_RESET 0x82000005
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/* Miscellaneous FID's' */
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#define MV_SIP_DRAM_SIZE 0x82000010
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#define MV_SIP_LLC_ENABLE 0x82000011
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#define MV_SIP_PMU_IRQ_ENABLE 0x82000012
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#define MV_SIP_PMU_IRQ_DISABLE 0x82000013
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#define MAX_LANE_NR 6
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#define MVEBU_COMPHY_OFFSET 0x441000
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#define MVEBU_SD_OFFSET 0x120000
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/* This macro is used to identify COMPHY related calls from SMC function ID */
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#define is_comphy_fid(fid) \
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((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET)
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uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags)
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{
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u_register_t ret;
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int i;
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debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
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__func__, smc_fid, x1, x2, x3);
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if (is_comphy_fid(smc_fid)) {
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/* some systems passes SD phys address instead of COMPHY phys
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* address - convert it
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*/
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if (x1 & MVEBU_SD_OFFSET)
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x1 = (x1 & ~0xffffff) + MVEBU_COMPHY_OFFSET;
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if ((x1 & 0xffffff) != MVEBU_COMPHY_OFFSET) {
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ERROR("%s: Wrong smc (0x%x) address: %lx\n",
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__func__, smc_fid, x1);
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SMC_RET1(handle, SMC_UNK);
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}
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if (x2 >= MAX_LANE_NR) {
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ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n",
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__func__, smc_fid, x2);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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switch (smc_fid) {
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/* Comphy related FID's */
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case MV_SIP_COMPHY_POWER_ON:
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/* x1: comphy_base, x2: comphy_index, x3: comphy_mode */
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ret = mvebu_cp110_comphy_power_on(x1, x2, x3);
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SMC_RET1(handle, ret);
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case MV_SIP_COMPHY_POWER_OFF:
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/* x1: comphy_base, x2: comphy_index */
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ret = mvebu_cp110_comphy_power_off(x1, x2, x3);
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SMC_RET1(handle, ret);
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case MV_SIP_COMPHY_PLL_LOCK:
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/* x1: comphy_base, x2: comphy_index */
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ret = mvebu_cp110_comphy_is_pll_locked(x1, x2);
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SMC_RET1(handle, ret);
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case MV_SIP_COMPHY_XFI_TRAIN:
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/* x1: comphy_base, x2: comphy_index */
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ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2);
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SMC_RET1(handle, ret);
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case MV_SIP_COMPHY_DIG_RESET:
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/* x1: comphy_base, x2: comphy_index, x3: mode, x4: command */
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ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4);
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SMC_RET1(handle, ret);
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/* Miscellaneous FID's' */
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case MV_SIP_DRAM_SIZE:
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/* x1: ap_base_addr */
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ret = mvebu_get_dram_size(x1);
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SMC_RET1(handle, ret);
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case MV_SIP_LLC_ENABLE:
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for (i = 0; i < ap_get_count(); i++)
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llc_runtime_enable(i);
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SMC_RET1(handle, 0);
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#ifdef MVEBU_PMU_IRQ_WA
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case MV_SIP_PMU_IRQ_ENABLE:
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mvebu_pmu_interrupt_enable();
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SMC_RET1(handle, 0);
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case MV_SIP_PMU_IRQ_DISABLE:
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mvebu_pmu_interrupt_disable();
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SMC_RET1(handle, 0);
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#endif
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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/* Define a runtime service descriptor for fast SMC calls */
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DECLARE_RT_SVC(
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marvell_sip_svc,
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OEN_SIP_START,
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OEN_SIP_END,
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SMC_TYPE_FAST,
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NULL,
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mrvl_sip_smc_handler
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);
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