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https://github.com/ARM-software/arm-trusted-firmware.git
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55df84f974
In Armada 8K DB boards, PCIe initialization can be executed only once because PCIe reset performed during chip power on and it cannot be executed via GPIO later. This means that power on can be executed only once, when it's called from the bootloader. Power on: Read bit 21 of the mode, it marks if the caller is the bootloader or the Linux Kernel. Power off: Check if the comphy was already configured to PCIe, if yes, check if the caller is bootloader, if both conditions are true (PCIe mode and called by Linux) - skip the power-off. In addition, fix incorrect documentation describing mode fields - PCIe width is 3 bits, not 2. NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work with it). Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
91 lines
2 KiB
C
91 lines
2 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* Those are parameters for xfi mode, which need to be tune for each board type.
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* For known DB boards the parameters was already calibrated and placed under
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* the plat/marvell/a8k/<board_type>/board/phy-porting-layer.h
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*/
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struct xfi_params {
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uint8_t g1_ffe_res_sel;
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uint8_t g1_ffe_cap_sel;
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uint8_t align90;
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uint8_t g1_dfe_res;
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uint8_t g1_amp;
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uint8_t g1_emph;
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uint8_t g1_emph_en;
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uint8_t g1_tx_amp_adj;
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uint8_t g1_tx_emph_en;
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uint8_t g1_tx_emph;
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uint8_t g1_rx_selmuff;
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uint8_t g1_rx_selmufi;
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uint8_t g1_rx_selmupf;
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uint8_t g1_rx_selmupi;
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_Bool valid;
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};
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struct sata_params {
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uint8_t g1_amp;
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uint8_t g2_amp;
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uint8_t g3_amp;
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uint8_t g1_emph;
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uint8_t g2_emph;
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uint8_t g3_emph;
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uint8_t g1_emph_en;
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uint8_t g2_emph_en;
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uint8_t g3_emph_en;
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uint8_t g1_tx_amp_adj;
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uint8_t g2_tx_amp_adj;
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uint8_t g3_tx_amp_adj;
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uint8_t g1_tx_emph_en;
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uint8_t g2_tx_emph_en;
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uint8_t g3_tx_emph_en;
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uint8_t g1_tx_emph;
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uint8_t g2_tx_emph;
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uint8_t g3_tx_emph;
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uint8_t g3_dfe_res;
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uint8_t g3_ffe_res_sel;
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uint8_t g3_ffe_cap_sel;
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uint8_t align90;
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uint8_t g1_rx_selmuff;
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uint8_t g2_rx_selmuff;
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uint8_t g3_rx_selmuff;
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uint8_t g1_rx_selmufi;
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uint8_t g2_rx_selmufi;
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uint8_t g3_rx_selmufi;
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uint8_t g1_rx_selmupf;
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uint8_t g2_rx_selmupf;
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uint8_t g3_rx_selmupf;
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uint8_t g1_rx_selmupi;
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uint8_t g2_rx_selmupi;
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uint8_t g3_rx_selmupi;
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_Bool valid;
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};
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int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
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uint8_t comphy_index);
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int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
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uint8_t comphy_index, uint64_t comphy_mode);
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int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
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uint8_t comphy_index, uint64_t comphy_mode);
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int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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uint8_t comphy_index);
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int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
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uint32_t comphy_mode, uint32_t command);
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