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https://github.com/ARM-software/arm-trusted-firmware.git
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6c8dda19e5
With the introduction of MPMM, the auxiliary AMU counter logic requires refactoring to move away from a single platform-defined group 1 counter mask in order to support microarchitectural (per-core) group 1 counters. BREAKING CHANGE: The `PLAT_AMU_GROUP1_COUNTERS_MASK` platform definition has been removed. Platforms should specify per-core AMU counter masks via FCONF or a platform-specific mechanism going forward. Change-Id: I1e852797c7954f92409222b066a1ae57bc72bb05 Signed-off-by: Chris Kay <chris.kay@arm.com>
110 lines
3.1 KiB
C
110 lines
3.1 KiB
C
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AMU_H
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#define AMU_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <lib/cassert.h>
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#include <lib/utils_def.h>
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#include <context.h>
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#include <platform_def.h>
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/* All group 0 counters */
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#define AMU_GROUP0_COUNTERS_MASK U(0xf)
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#define AMU_GROUP0_NR_COUNTERS U(4)
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#define AMU_GROUP1_COUNTERS_MASK U(0)
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/* Calculate number of group 1 counters */
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#if (AMU_GROUP1_COUNTERS_MASK & (1 << 15))
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#define AMU_GROUP1_NR_COUNTERS 16U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14))
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#define AMU_GROUP1_NR_COUNTERS 15U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13))
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#define AMU_GROUP1_NR_COUNTERS 14U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12))
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#define AMU_GROUP1_NR_COUNTERS 13U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11))
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#define AMU_GROUP1_NR_COUNTERS 12U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10))
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#define AMU_GROUP1_NR_COUNTERS 11U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9))
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#define AMU_GROUP1_NR_COUNTERS 10U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8))
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#define AMU_GROUP1_NR_COUNTERS 9U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7))
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#define AMU_GROUP1_NR_COUNTERS 8U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6))
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#define AMU_GROUP1_NR_COUNTERS 7U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5))
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#define AMU_GROUP1_NR_COUNTERS 6U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4))
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#define AMU_GROUP1_NR_COUNTERS 5U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3))
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#define AMU_GROUP1_NR_COUNTERS 4U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2))
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#define AMU_GROUP1_NR_COUNTERS 3U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1))
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#define AMU_GROUP1_NR_COUNTERS 2U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0))
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#define AMU_GROUP1_NR_COUNTERS 1U
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#else
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#define AMU_GROUP1_NR_COUNTERS 0U
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#endif
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CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask);
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
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#if __aarch64__
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/* Architected event counter 1 does not have an offset register. */
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uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1];
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#endif
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#if AMU_GROUP1_NR_COUNTERS
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uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
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#if __aarch64__
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uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS];
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#endif
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#endif
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};
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unsigned int amu_get_version(void);
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#if __aarch64__
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void amu_enable(bool el2_unused, cpu_context_t *ctx);
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#else
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void amu_enable(bool el2_unused);
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#endif
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/* Group 0 configuration helpers */
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uint64_t amu_group0_cnt_read(unsigned int idx);
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void amu_group0_cnt_write(unsigned int idx, uint64_t val);
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#if __aarch64__
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uint64_t amu_group0_voffset_read(unsigned int idx);
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void amu_group0_voffset_write(unsigned int idx, uint64_t val);
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#endif
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#if AMU_GROUP1_NR_COUNTERS
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bool amu_group1_supported(void);
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/* Group 1 configuration helpers */
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uint64_t amu_group1_cnt_read(unsigned int idx);
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void amu_group1_cnt_write(unsigned int idx, uint64_t val);
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void amu_group1_set_evtype(unsigned int idx, unsigned int val);
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#if __aarch64__
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uint64_t amu_group1_voffset_read(unsigned int idx);
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void amu_group1_voffset_write(unsigned int idx, uint64_t val);
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#endif
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#endif
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#endif /* AMU_H */
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