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6ba97f83db
The current definitions of reference clock speed register values #define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M #define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M is ambiguous. The name of the constant implies 25 MHz, but the value implies 30 MHz, which may make the reader think that the setting has something to do with both values. In reality, the values have different tables for SerDes and PCIe/USB3 PHY mode. The value for 25 MHz for PCIe/USB3 mode (0x2) is the value for 30 MHz for SerDes mode. Instead of defining the PCIe/USB3 constants relative to SerDes constants, define them with absolute values, thus making it a little bit more obvious that different modes have different value tables. Signed-off-by: Marek Behún <marek.behun@nic.cz> Change-Id: I50c66c6bbe22b9a9bec4685600cb8560524a643c |
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| .. | ||
| comphy | ||
| mc_trustzone | ||
| mg_conf_cm3 | ||
| mochi | ||
| secure_dfx_access | ||
| uart | ||
| amb_adec.c | ||
| ap807_clocks_init.c | ||
| cache_llc.c | ||
| ccu.c | ||
| comphy.h | ||
| ddr_phy_access.c | ||
| ddr_phy_access.h | ||
| gwin.c | ||
| io_win.c | ||
| iob.c | ||
| mci.c | ||
| thermal.c | ||