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As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/spinlock.h>
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#include "fpga_private.h"
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#include <plat/common/platform.h>
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#include <platform_def.h>
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unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2];
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unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT];
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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unsigned int i;
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/*
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* The highest level is the system level. The next level is constituted
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* by clusters and then cores in clusters.
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*
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* This description of the power domain topology is aligned with the CPU
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* indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos()
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* APIs.
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*
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* A description of the topology tree can be found at
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* https://trustedfirmware-a.readthedocs.io/en/latest/design/psci-pd-tree.html#design
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*/
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if (fpga_power_domain_tree_desc[0] == 0U) {
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/*
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* As fpga_power_domain_tree_desc[0] == 0, assume that the
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* Power Domain Topology Tree has not been initialized, so
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* perform the initialization here.
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*/
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fpga_power_domain_tree_desc[0] = 1U;
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fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT;
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for (i = 0U; i < FPGA_MAX_CLUSTER_COUNT; i++) {
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fpga_power_domain_tree_desc[2 + i] =
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(FPGA_MAX_CPUS_PER_CLUSTER *
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FPGA_MAX_PE_PER_CPU);
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}
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}
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return fpga_power_domain_tree_desc;
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}
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int core_pos;
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mpidr &= (MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT));
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mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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if ((MPIDR_AFFLVL2_VAL(mpidr) >= FPGA_MAX_CLUSTER_COUNT) ||
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(MPIDR_AFFLVL1_VAL(mpidr) >= FPGA_MAX_CPUS_PER_CLUSTER) ||
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(MPIDR_AFFLVL0_VAL(mpidr) >= FPGA_MAX_PE_PER_CPU)) {
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ERROR ("Invalid mpidr: 0x%08x\n", (uint32_t)mpidr);
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panic();
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}
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/* Calculate the core position, based on the maximum topology. */
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core_pos = plat_fpga_calc_core_pos(mpidr);
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/* Check whether this core is actually present. */
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if (fpga_valid_mpids[core_pos] != VALID_MPID) {
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return -1;
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}
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return core_pos;
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}
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