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Ensure (where possible) that switch statements in drivers comply with MISRA rules 16.1 - 16.7. Change-Id: I7a91e04b02af80fbc4673a52293386c0f81a0f7a Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
170 lines
3.8 KiB
C
170 lines
3.8 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <assert.h>
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#include <cci.h>
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#include <debug.h>
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#include <mmio.h>
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#include <stdint.h>
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#define MAKE_CCI_PART_NUMBER(hi, lo) ((hi << 8) | lo)
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#define CCI_PART_LO_MASK 0xff
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#define CCI_PART_HI_MASK 0xf
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/* CCI part number codes read from Peripheral ID registers 0 and 1 */
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#define CCI400_PART_NUM 0x420
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#define CCI500_PART_NUM 0x422
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#define CCI550_PART_NUM 0x423
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#define CCI400_SLAVE_PORTS 5
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#define CCI500_SLAVE_PORTS 7
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#define CCI550_SLAVE_PORTS 7
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static uintptr_t cci_base;
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static const int *cci_slave_if_map;
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#if ENABLE_ASSERTIONS
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static unsigned int max_master_id;
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static int cci_num_slave_ports;
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static int validate_cci_map(const int *map)
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{
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unsigned int valid_cci_map = 0;
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int slave_if_id;
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int i;
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/* Validate the map */
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for (i = 0; i <= max_master_id; i++) {
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slave_if_id = map[i];
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if (slave_if_id < 0)
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continue;
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if (slave_if_id >= cci_num_slave_ports) {
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ERROR("Slave interface ID is invalid\n");
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return 0;
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}
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if (valid_cci_map & (1 << slave_if_id)) {
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ERROR("Multiple masters are assigned same slave interface ID\n");
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return 0;
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}
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valid_cci_map |= 1 << slave_if_id;
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}
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if (!valid_cci_map) {
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ERROR("No master is assigned a valid slave interface\n");
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return 0;
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}
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return 1;
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}
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/*
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* Read CCI part number from Peripheral ID registers
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*/
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static unsigned int read_cci_part_number(uintptr_t base)
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{
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unsigned int part_lo, part_hi;
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part_lo = mmio_read_32(base + PERIPHERAL_ID0) & CCI_PART_LO_MASK;
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part_hi = mmio_read_32(base + PERIPHERAL_ID1) & CCI_PART_HI_MASK;
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return MAKE_CCI_PART_NUMBER(part_hi, part_lo);
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}
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/*
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* Identify a CCI device, and return the number of slaves. Return -1 for an
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* unidentified device.
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*/
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static int get_slave_ports(unsigned int part_num)
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{
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int num_slave_ports = -1;
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switch (part_num) {
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case CCI400_PART_NUM:
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num_slave_ports = CCI400_SLAVE_PORTS;
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break;
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case CCI500_PART_NUM:
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num_slave_ports = CCI500_SLAVE_PORTS;
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break;
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case CCI550_PART_NUM:
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num_slave_ports = CCI550_SLAVE_PORTS;
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return num_slave_ports;
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}
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#endif /* ENABLE_ASSERTIONS */
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void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters)
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{
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assert(map);
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assert(base);
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cci_base = base;
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cci_slave_if_map = map;
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#if ENABLE_ASSERTIONS
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/*
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* Master Id's are assigned from zero, So in an array of size n
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* the max master id is (n - 1).
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*/
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max_master_id = num_cci_masters - 1;
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cci_num_slave_ports = get_slave_ports(read_cci_part_number(base));
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#endif
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assert(cci_num_slave_ports >= 0);
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assert(validate_cci_map(map));
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}
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void cci_enable_snoop_dvm_reqs(unsigned int master_id)
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{
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int slave_if_id = cci_slave_if_map[master_id];
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assert(master_id <= max_master_id);
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assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
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assert(cci_base);
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/*
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* Enable Snoops and DVM messages, no need for Read/Modify/Write as
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* rest of bits are write ignore
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*/
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mmio_write_32(cci_base +
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SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
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DVM_EN_BIT | SNOOP_EN_BIT);
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/* Wait for the dust to settle down */
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while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
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;
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}
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void cci_disable_snoop_dvm_reqs(unsigned int master_id)
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{
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int slave_if_id = cci_slave_if_map[master_id];
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assert(master_id <= max_master_id);
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assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
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assert(cci_base);
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/*
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* Disable Snoops and DVM messages, no need for Read/Modify/Write as
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* rest of bits are write ignore.
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*/
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mmio_write_32(cci_base +
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SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
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~(DVM_EN_BIT | SNOOP_EN_BIT));
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/* Wait for the dust to settle down */
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while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
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;
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}
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