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https://github.com/ARM-software/arm-trusted-firmware.git
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6a367fd1ef
This patch fixes the delay loop used to wake up the BPMP during SC7 exit. The earlier loop would fail just when the timer was about to wrap-around (e.g. when TEGRA_TMRUS_BASE is 0xfffffffe, the target value becomes 0, which would cause the loop to exit before it's expiry). Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
241 lines
8 KiB
C
241 lines
8 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <delay_timer.h>
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#include <mmio.h>
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#include <pmc.h>
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#include <cortex_a53.h>
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#include <flowctrl.h>
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#include <tegra_def.h>
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#define CLK_RST_DEV_L_SET 0x300
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#define CLK_RST_DEV_L_CLR 0x304
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#define CLK_BPMP_RST (1 << 1)
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#define EVP_BPMP_RESET_VECTOR 0x200
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static const uint64_t flowctrl_offset_cpu_csr[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16)
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};
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static const uint64_t flowctrl_offset_halt_cpu[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16)
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};
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static const uint64_t flowctrl_offset_cc4_ctrl[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12)
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};
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static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]);
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}
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static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]);
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}
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static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]);
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}
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static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr)
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{
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uint32_t val;
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val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ |
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FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ |
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FLOWCTRL_WAITEVENT;
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tegra_fc_halt_cpu(cpu_id, val);
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val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
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FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id);
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tegra_fc_cpu_csr(cpu_id, val | csr);
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}
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/*******************************************************************************
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* Suspend the current CPU
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******************************************************************************/
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void tegra_fc_cpu_idle(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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VERBOSE("CPU%d powering down...\n", cpu);
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tegra_fc_prepare_suspend(cpu, 0);
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}
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/*******************************************************************************
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* Suspend the current CPU cluster
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******************************************************************************/
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void tegra_fc_cluster_idle(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering cluster idle state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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/* hardware L2 flush is faster for A53 only */
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL,
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!!MPIDR_AFFLVL1_VAL(mpidr));
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/* suspend the CPU cluster */
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val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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}
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/*******************************************************************************
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* Power down the current CPU cluster
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******************************************************************************/
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void tegra_fc_cluster_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering cluster powerdn state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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/* hardware L2 flush is faster for A53 only */
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL,
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read_midr() == CORTEX_A53_MIDR);
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/* power down the CPU cluster */
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val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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}
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/*******************************************************************************
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* Suspend the entire SoC
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******************************************************************************/
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void tegra_fc_soc_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering SoC powerdn state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1);
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val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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/* overwrite HALT register */
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT);
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}
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/*******************************************************************************
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* Power up the CPU
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******************************************************************************/
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void tegra_fc_cpu_on(int cpu)
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{
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tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE);
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK);
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}
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/*******************************************************************************
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* Power down the CPU
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******************************************************************************/
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void tegra_fc_cpu_off(int cpu)
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{
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uint32_t val;
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/*
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* Flow controller powers down the CPU during wfi. The CPU would be
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* powered on when it receives any interrupt.
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*/
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val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
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FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu);
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tegra_fc_cpu_csr(cpu, val);
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT);
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tegra_fc_cc4_ctrl(cpu, 0);
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}
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/*******************************************************************************
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* Inform the BPMP that we have completed the cluster power up
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******************************************************************************/
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void tegra_fc_lock_active_cluster(void)
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{
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uint32_t val;
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val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
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val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK;
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tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val);
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val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
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}
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/*******************************************************************************
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* Reset BPMP processor
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******************************************************************************/
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void tegra_fc_reset_bpmp(void)
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{
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uint32_t val;
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/* halt BPMP */
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tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT);
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/* Assert BPMP reset */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST);
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/* Restore reset address (stored in PMC_SCRATCH39) */
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val = tegra_pmc_read_32(PMC_SCRATCH39);
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mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, val);
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while (val != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR))
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; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
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/* Wait for 2us before de-asserting the reset signal. */
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udelay(2);
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/* De-assert BPMP reset */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST);
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/* Un-halt BPMP */
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tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0);
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}
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