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https://github.com/ARM-software/arm-trusted-firmware.git
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d20fa4e4e0
Also, convert checker functions of errata which are enabled for all cpu revisions to report correctly in preparation of the errata ABI. Although the script from commit 250919 was used to check that errata code did not change, this CPU only loosely adhered to convention and its output was not particularly useful. Nevertheless, the discrepancies were manually verified. All errata have been checked that they get invoked. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I988db6e7b6d1732f1d2258dbdf945cb475781894
230 lines
7.2 KiB
ArmAsm
230 lines
7.2 KiB
ArmAsm
/*
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* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a53.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include <lib/cpus/errata.h>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a53_disable_dcache
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sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
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isb
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ret
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endfunc cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a53_disable_smp
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sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT
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isb
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dsb sy
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ret
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endfunc cortex_a53_disable_smp
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1)
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2)
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319
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mrs x1, CORTEX_A53_L2ACTLR_EL1
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bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
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orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
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msr CORTEX_A53_L2ACTLR_EL1, x1
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workaround_reset_end cortex_a53, ERRATUM(826319)
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check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2)
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2)
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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check_erratum_custom_start cortex_a53, ERRATUM(835769)
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cmp x0, CPU_REV(0, 4)
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b.hi errata_not_applies
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/*
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* Fix potentially available for revisions r0p2, r0p3 and r0p4.
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* If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit.
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*/
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cmp x0, #0x01
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mov x0, #ERRATA_APPLIES
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b.ls exit_check_errata_835769
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/* Load REVIDR. */
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mrs x1, revidr_el1
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/* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */
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tbz x1, #7, exit_check_errata_835769
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errata_not_applies:
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mov x0, #ERRATA_NOT_APPLIES
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exit_check_errata_835769:
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ret
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check_erratum_custom_end cortex_a53, ERRATUM(835769)
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/* workaround at build time */
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add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET
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/*
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* Disable the cache non-temporal hint.
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*
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* This ignores the Transient allocation hint in the MAIR and treats
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* allocations the same as non-transient allocation types. As a result,
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* the LDNP and STNP instructions in AArch64 behave the same as the
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* equivalent LDP and STP instructions.
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*/
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workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT
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sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH
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workaround_reset_end cortex_a53, ERRATUM(836870)
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check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3)
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check_erratum_custom_start cortex_a53, ERRATUM(843419)
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mov x1, #ERRATA_APPLIES
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mov x2, #ERRATA_NOT_APPLIES
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cmp x0, CPU_REV(0, 4)
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csel x0, x1, x2, ls
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/*
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* Fix potentially available for revision r0p4.
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* If r0p4 check for fix in REVIDR, else exit.
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*/
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b.ne exit_check_errata_843419
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/* Load REVIDR. */
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mrs x3, revidr_el1
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/* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */
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tbz x3, #8, exit_check_errata_843419
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mov x0, x2
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exit_check_errata_843419:
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ret
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check_erratum_custom_end cortex_a53, ERRATUM(843419)
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/* workaround at build time */
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add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET
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/*
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* Earlier revisions of the core are affected as well, but don't
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* have the chicken bit in the CPUACTLR register. It is expected that
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* the rich OS takes care of that, especially as the workaround is
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* shared with other erratas in those revisions of the CPU.
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*/
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workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873
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sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
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workaround_reset_end cortex_a53, ERRATUM(855873)
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check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3)
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check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924
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/* erratum has no workaround in the cpu. Generic code must take care */
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add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET
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cpu_reset_func_start cortex_a53
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/* Enable the SMP bit. */
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sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT
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cpu_reset_func_end cortex_a53
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func cortex_a53_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a53_disable_smp
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endfunc cortex_a53_core_pwr_dwn
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func cortex_a53_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a53_disable_smp
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endfunc cortex_a53_cluster_pwr_dwn
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errata_report_shim cortex_a53
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/* ---------------------------------------------
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* This function provides cortex_a53 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a53_regs, "aS"
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cortex_a53_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \
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"cpuactlr_el1", ""
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func cortex_a53_cpu_reg_dump
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adr x6, cortex_a53_regs
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mrs x8, CORTEX_A53_ECTLR_EL1
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mrs x9, CORTEX_A53_MERRSR_EL1
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mrs x10, CORTEX_A53_L2MERRSR_EL1
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mrs x11, CORTEX_A53_CPUACTLR_EL1
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ret
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endfunc cortex_a53_cpu_reg_dump
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
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cortex_a53_reset_func, \
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cortex_a53_core_pwr_dwn, \
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cortex_a53_cluster_pwr_dwn
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