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https://github.com/ARM-software/arm-trusted-firmware.git
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67412e4d7a
For somewhat historical reasons we are doing some initial PMIC regulator setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked fine so far, but there is at least one board (OrangePi 3) that gets upset, because the Ethernet PHY needs some *coordinated* bringup of *two* regulators. To avoid custom hacks, let's introduce a build option to keep doing the regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break support for some devices on some boards in U-Boot (Ethernet and HDMI), but will allow to bring up the OrangePi 3 in Linux correctly. We keep the default at 1 to not change the behaviour for all other boards. After U-Boot gained proper PMIC support at some point in the future, we will probably change the default to 0, to get rid of the less optimal PMIC code in TF-A. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
96 lines
3 KiB
Makefile
96 lines
3 KiB
Makefile
#
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# Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/xlat_tables_v2/xlat_tables.mk
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include lib/libfdt/libfdt.mk
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include drivers/arm/gic/v2/gicv2.mk
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AW_PLAT := plat/allwinner
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PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
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-I${AW_PLAT}/common/include \
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-I${AW_PLAT}/${PLAT}/include
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PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \
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${XLAT_TABLES_LIB_SRCS} \
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${AW_PLAT}/common/plat_helpers.S \
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${AW_PLAT}/common/sunxi_common.c
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BL31_SOURCES += drivers/allwinner/axp/common.c \
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${GICV2_SOURCES} \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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lib/cpus/${ARCH}/cortex_a53.S \
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plat/common/plat_gicv2.c \
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plat/common/plat_psci_common.c \
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${AW_PLAT}/common/sunxi_bl31_setup.c \
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${AW_PLAT}/common/sunxi_pm.c \
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${AW_PLAT}/${PLAT}/sunxi_power.c \
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${AW_PLAT}/common/sunxi_security.c \
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${AW_PLAT}/common/sunxi_topology.c
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# By default, attempt to use SCPI to the ARISC management processor. If SCPI
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# is not enabled or SCP firmware is not loaded, fall back to a simpler native
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# implementation that does not support CPU or system suspend.
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#
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# If SCP firmware will always be present (or absent), the unused implementation
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# can be compiled out.
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SUNXI_PSCI_USE_NATIVE ?= 1
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SUNXI_PSCI_USE_SCPI ?= 1
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$(eval $(call assert_boolean,SUNXI_PSCI_USE_NATIVE))
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$(eval $(call assert_boolean,SUNXI_PSCI_USE_SCPI))
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$(eval $(call add_define,SUNXI_PSCI_USE_NATIVE))
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$(eval $(call add_define,SUNXI_PSCI_USE_SCPI))
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ifeq (${SUNXI_PSCI_USE_NATIVE}${SUNXI_PSCI_USE_SCPI},00)
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$(error "At least one of SCPI or native PSCI ops must be enabled")
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endif
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ifeq (${SUNXI_PSCI_USE_NATIVE},1)
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BL31_SOURCES += ${AW_PLAT}/common/sunxi_cpu_ops.c \
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${AW_PLAT}/common/sunxi_native_pm.c
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endif
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ifeq (${SUNXI_PSCI_USE_SCPI},1)
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BL31_SOURCES += drivers/allwinner/sunxi_msgbox.c \
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drivers/arm/css/scpi/css_scpi.c \
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${AW_PLAT}/common/sunxi_scpi_pm.c
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endif
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SUNXI_SETUP_REGULATORS ?= 1
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$(eval $(call assert_boolean,SUNXI_SETUP_REGULATORS))
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$(eval $(call add_define,SUNXI_SETUP_REGULATORS))
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# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
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COLD_BOOT_SINGLE_CPU := 1
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# Do not enable SPE (not supported on ARM v8.0).
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ENABLE_SPE_FOR_LOWER_ELS := 0
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# Do not enable SVE (not supported on ARM v8.0).
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ENABLE_SVE_FOR_NS := 0
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# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
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ERRATA_A53_835769 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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ERRATA_A53_1530924 := 1
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# The traditional U-Boot load address is 160MB into DRAM.
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PRELOADED_BL33_BASE ?= 0x4a000000
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# The reset vector can be changed for each CPU.
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PROGRAMMABLE_RESET_ADDRESS := 1
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# Allow mapping read-only data as execute-never.
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SEPARATE_CODE_AND_RODATA := 1
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# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
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RESET_TO_BL31 := 1
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# This platform is single-cluster and does not require coherency setup.
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WARMBOOT_ENABLE_DCACHE_EARLY := 1
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