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672eb21e26
Cortex-A78C erratum 1827430 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set the CPUECTLR_EL1[53] to 1, which disables allocation of splintered pages in the L2 TLB. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426
369 lines
9.6 KiB
ArmAsm
369 lines
9.6 KiB
ArmAsm
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78c.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for A78C Erratum 1827430.
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* This applies to revision r0p0 of the Cortex A78C
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* processor and is fixed in r0p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78c_1827430_wa
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mov x17, x30
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bl check_errata_1827430
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cbz x0, 1f
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/* Disable allocation of splintered pages in the L2 TLB */
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mrs x1, CORTEX_A78C_CPUECTLR_EL1
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orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
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msr CORTEX_A78C_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a78c_1827430_wa
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func check_errata_1827430
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/* Applies to revision r0p0 only */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_1827430
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78C Erratum 2376749.
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* This applies to revision r0p1 and r0p2 of the A78C
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* and is currently open. It is a Cat B erratum.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x4, x17
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* --------------------------------------------------
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*/
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func errata_a78c_2376749_wa
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/* Check revision */
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mov x17, x30
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bl check_errata_2376749
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cbz x0, 1f
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/* Set CPUACTLR2_EL1[0] to 1. */
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mrs x1, CORTEX_A78C_CPUACTLR2_EL1
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orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
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msr CORTEX_A78C_CPUACTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_a78c_2376749_wa
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func check_errata_2376749
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/* Applies to r0p1 and r0p2*/
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mov x1, #0x01
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mov x2, #0x02
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b cpu_rev_var_range
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endfunc check_errata_2376749
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78C Erratum 2395411.
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* This applies to revision r0p1 and r0p2 of the A78C
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* and is currently open. It is a Cat B erratum.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x4, x17
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* --------------------------------------------------
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*/
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func errata_a78c_2395411_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2395411
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cbz x0, 1f
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/* Set CPUACTRL2_EL1[40] to 1. */
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mrs x1, CORTEX_A78C_CPUACTLR2_EL1
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orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40
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msr CORTEX_A78C_CPUACTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_a78c_2395411_wa
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func check_errata_2395411
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/* Applies to r0p1 and r0p2 */
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mov x1, #0x01
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mov x2, #0x02
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b cpu_rev_var_range
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endfunc check_errata_2395411
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for A78C Erratum 2132064.
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* This applies to revisions r0p1 and r0p2 of A78C
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* and is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78c_2132064_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_2132064
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cbz x0, 1f
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/* --------------------------------------------------------
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* Place the data prefetcher in the most conservative mode
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* to reduce prefetches by writing the following bits to
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* the value indicated: ecltr[7:6], PF_MODE = 2'b11
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* --------------------------------------------------------
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*/
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mrs x0, CORTEX_A78C_CPUECTLR_EL1
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orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6
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orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7
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msr CORTEX_A78C_CPUECTLR_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78c_2132064_wa
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func check_errata_2132064
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/* Applies to revisions r0p1 and r0p2. */
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mov x1, #CPU_REV(0, 1)
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mov x2, #CPU_REV(0, 2)
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b cpu_rev_var_range
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endfunc check_errata_2132064
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/* ----------------------------------------------------------
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* Errata Workaround for A78C Erratum 2242638.
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* This applies to revisions r0p1 and r0p2 of the Cortex A78C
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* processor and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ----------------------------------------------------------
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*/
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func errata_a78c_2242638_wa
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/* Compare x0 against revisions r0p1 - r0p2 */
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mov x17, x30
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bl check_errata_2242638
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cbz x0, 1f
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ldr x0, =0x5
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msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
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ldr x0, =0x10F600E000
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msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
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ldr x0, =0x10FF80E000
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msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
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ldr x0, =0x80000000003FF
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msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_a78c_2242638_wa
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func check_errata_2242638
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/* Applies to revisions r0p1-r0p2. */
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mov x1, #CPU_REV(0, 1)
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mov x2, #CPU_REV(0, 2)
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b cpu_rev_var_range
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endfunc check_errata_2242638
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/* ----------------------------------------------------------------
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* Errata Workaround for A78C Erratum 2772121.
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* This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
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* processor and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ----------------------------------------------------------------
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*/
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func errata_a78c_2772121_wa
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mov x17, x30
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bl check_errata_2772121
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cbz x0, 1f
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/* dsb before isb of power down sequence */
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dsb sy
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1:
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ret x17
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endfunc errata_a78c_2772121_wa
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func check_errata_2772121
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/* Applies to all revisions <= r0p2 */
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mov x1, #0x02
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b cpu_rev_var_ls
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endfunc check_errata_2772121
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78C Errata 2779484.
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* This applies to revisions r0p1 and r0p2.
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* It is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_a78c_2779484_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2779484
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cbz x0, 1f
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/* Apply the workaround */
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mrs x1, CORTEX_A78C_ACTLR3_EL1
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orr x1, x1, #BIT(47)
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msr CORTEX_A78C_ACTLR3_EL1, x1
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1:
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ret x17
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endfunc errata_a78c_2779484_wa
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func check_errata_2779484
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/* Applies to r0p1 and r0p2*/
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mov x1, #0x01
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mov x2, #0x02
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b cpu_rev_var_range
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endfunc check_errata_2779484
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78C
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* -------------------------------------------------
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*/
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func cortex_a78c_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A78C_1827430
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mov x0, x18
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bl errata_a78c_1827430_wa
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#endif
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#if ERRATA_A78C_2132064
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mov x0, x18
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bl errata_a78c_2132064_wa
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#endif
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#if ERRATA_A78C_2242638
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mov x0, x18
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bl errata_a78c_2242638_wa
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#endif
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#if ERRATA_A78C_2376749
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mov x0, x18
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bl errata_a78c_2376749_wa
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#endif
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#if ERRATA_A78C_2395411
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mov x0, x18
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bl errata_a78c_2395411_wa
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#endif
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#if ERRATA_A78C_2779484
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mov x0, x18
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bl errata_a78c_2779484_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A78c generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a78c
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret x19
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endfunc cortex_a78c_reset_func
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a78c_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
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#if ERRATA_A78C_2772121
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mov x15, x30
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bl cpu_get_rev_var
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bl errata_a78c_2772121_wa
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mov x30, x15
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#endif /* ERRATA_A78C_2772121 */
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isb
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ret
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endfunc cortex_a78c_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A78C. Must follow AAPCS.
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*/
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func cortex_a78c_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430
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report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
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report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
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report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
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report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
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report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
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report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a78c_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a78c specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a78c_regs, "aS"
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cortex_a78c_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78c_cpu_reg_dump
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adr x6, cortex_a78c_regs
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mrs x8, CORTEX_A78C_CPUECTLR_EL1
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ret
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endfunc cortex_a78c_cpu_reg_dump
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declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
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cortex_a78c_reset_func, \
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cortex_a78c_core_pwr_dwn
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