Bipin Ravi 672eb21e26 fix(cpus): workaround for Cortex-A78C erratum 1827430 ... Cortex-A78C erratum 1827430 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set the CPUECTLR_EL1[53] to 1, which disables allocation of splintered pages in the L2 TLB. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Ie68771bdd3bddeff54d06b6a456dad4a7fc27426		2023-03-21 16:14:41 -05:00
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aarch32	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00
aarch64	fix(cpus): workaround for Cortex-A78C erratum 1827430	2023-03-21 16:14:41 -05:00
errata_report.h	Workaround for Cortex A78 erratum 1951500	2021-01-13 13:54:18 -06:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2022_23960.h	fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57	2022-03-18 01:01:34 +02:00