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https://github.com/ARM-software/arm-trusted-firmware.git
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f2596ff1a8
TC2 and TC3 have different the scmi shared memory regions and MHU parameters, this patch appends the properties in scmi node for TC2 and TC3 respectively. Change-Id: Ifd001f780b575987877b4be36eb755a9dbe57e60 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>
88 lines
1.8 KiB
Text
88 lines
1.8 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <platform_def.h>
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#define LIT_CAPACITY 239
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#define MID_CAPACITY 686
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#define BIG_CAPACITY 1024
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#define MHU_TX_ADDR 46040000 /* hex */
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#define MHU_TX_COMPAT "arm,mhuv3"
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#define MHU_TX_INT_NAME ""
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#define MHU_RX_ADDR 46140000 /* hex */
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#define MHU_RX_COMPAT "arm,mhuv3"
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#define MHU_OFFSET 0x10000
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#define MHU_MBOX_CELLS 3
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#define MHU_RX_INT_NUM 300
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#define MHU_RX_INT_NAME "combined-mbx"
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#define UARTCLK_FREQ 3750000
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#if TARGET_FLAVOUR_FVP
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#define DPU_ADDR 4000000000
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#define DPU_IRQ 579
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#elif TARGET_FLAVOUR_FPGA
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#define DPU_ADDR 2cc00000
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#define DPU_IRQ 69
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#endif
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#include "tc-common.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc-fvp.dtsi"
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#else
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#include "tc-fpga.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc-base.dtsi"
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/ {
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cpus {
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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};
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cpu-pmu {
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interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
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};
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sram: sram@6000000 {
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cpu_scp_scmi_p2a: scp-shmem@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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};
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firmware {
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scmi {
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mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
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shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
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};
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};
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};
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